This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LM76002: Deglitch Time for Power Good

Part Number: LM76002

In the E/C table, the deglitch time is 140uS,typ. But in the 7.3.11 it says the deglitch time is 220uS. We're a little confused on this.

and we don't see any timing plot with power good and its deglitch time. is that possibly to offer it for more clear behavior? and what's the purpose of the deglitch time, please offer an example?

Regards

Brian W

  • hi, Brian,

    I have double check on LMR76005 datasheet, it should be 140us.  page 18  "Both rising and falling edges of the power-good flag have a built-in 140-µs (typical) deglitch delay " .

    Purpose of the deglitch time is , prevent FB ringing goes to low in a very short time, that will get a wrong PGOOD H/L result.

    Sorry I don't have a waveform in LMR76002, but I have below,  is FB and PG plot for reference.

    Elena