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LM3423-Q1: LM3423-Q1 Dimming frequency

Stijn Bosmans
Prodigy 225 points
Part Number: LM3423-Q1
Other Parts Discussed in Thread: LM3423

Hi all,

For a design we are planning to use the LM3423-Q1 to drive the currents. Our goal is to use the IC/design for PWM dimming via the nDIM pin.

Design details:

  • Vin=28V
  • Vout=60V
  • ILED=2A
  • Series NFET with the LEDs
  • ELCO buffer cap at input

In the AN-2011 application note of the design the next statements are made:

"In general, contrast ratios much above 4000:1 are not possible for any operating point using the LM3423 boost evaluation board."

"A total value of 40 µF (using 4 10 µF ceramic capacitors) is chosen to improve PWM dimming response therefore the actual ΔiLED-PP is:"

We have the request to apply a low PWM frequency on the nDIM pin(1-10Hz with an ON-time of a couple of us - 40us). This will cause a contrast ratio much higher than stated in the application note.Currently, we don't understand why the contrast ratio is limited at  4000:1.

We understand that the system will be disabled during the OFF-state of the nDIM. In this OFF-state the voltage level at the output(at the output capacitors) will only discharge over the OVP resistors if we are correct. So when choosing the right capacitors/OVP resistor divider the voltage loss over at the output should be limited during the OFF time. Can you provide some more details why the contrast ratio is limited?

Also we have seen the recommendations of 40uF as an output capacitance. But also here we are looking for the explanation for this. I think this is linked to the question above.

Thanks in advance, 
Stijn

  • 0
    TI__Mastermind 18890 points

    Hello Stijn,

    As stated for  PWM dimming frequency of 120Hz to 25KHz the dimming, the duty contrast ratio of 20:1 for 25KHz represent dimming period of is about 2uS.  For the 120Hz case the dimming of 2500:1 is also period of 2uS.  So the limiting narrow period that this evaluation board can achieve is 2uS.  So when we mentioned the contrast ratio of 4000:1 this applies to the stated design of 120Hz dimming frequency.  You can get lower PWM dimming range if the PWM dimming frequency is decreased.   

    As far as the output capacitance is concerned:  During PWM dimming OFF time the current in the inductor will drop to 0A and when PWM dimming is ON the current has to ramp up in the inductor first and this time depends on the input voltage and power stage design to supply the output current.  During this ramp of current the output cap has to provide the current to the load.  That's why using larger caps will help with handling the initial current to the LED.

    The application note for the evaluation board is only design and shown for certain input and output range and the 2uS mention above for dimming is only applicable to that design.  For your design, it will be tough to get down to 2uS dimming at the power and voltage level you are requesting. 

    Thanks Tuan