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UCC21750-Q1: ISO5852SQDWRQ1

Part Number: UCC21750-Q1

The response to the copper under the gate driver body was very interesting. I have a related question involving SiCMOS devices in a TO-247-4 package – see image. Space limitations and the orientation of the liquid cooled heat sink coupled with the goal of keeping power loop inductance and gate loop inductance at a minimum suggests a component placement as shown.  What affects does the magnetic field developed by the SiCMOS have on the gate driver?  Thanks, Merrill

  • What affects does the magnetic field developed by the SiCMOS have on the gate driver? 

    Bud, nice to hear from you again. 

    This is effect is very hard to predict. It depends so much on the direction and magntiude of the field and highly dependent on direction of current and position.
    High EMI will cause all drivers regardless of mfr to behave unpredictably at some point, but the threshold is not possibly to quantify due to so many dependent factors. 

    I think the TO247-4 is not to scale so its not extending over to the cold-side. 

    We would recommend to place a Source/GND2 copper plane between the sicfet body and the underside of the driver die on one of the inner layers if this is your use case. 

    Please let me know if you have any more questions on this. 

    Best

    Dimitri