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TPS7A8300: Voltage Leak At Output Before LDO is ON

Part Number: TPS7A8300
Other Parts Discussed in Thread: TPS7A85, TPS7A84

Hi TI Team,

I have a question on TPS7A8300

We have power supply rail as above.

First of all the 1.5V is output from buck converter, and then ANALOG_0.9V is enabled before ANALOG_1.2V, and the FPGA leaked the voltage before ANALOG_1.2V is enabled.

So we have the ON and OFF waveform as below. There is some leakage at ANALOG_1.2V but it does not exceed 0.9V.

My question is;

Will this leakage give any effect to the ANALOG_1.2V LDO in terms of operability and reliabilty?

We dont want to add additional load switch or change the LDO due to design constraint.

Best Regards