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TPIC44H01: Question on the Over-supply voltage lockout feature

Part Number: TPIC44H01

Hi,

I am currently looking for a Quad (or Octal) high side driver that can support line voltage up to 32V.

I have checked the TPIC44H01 datasheet and noticed that the OVLO would set it at a minimum of 27.5V but the VPWR should survive up to 40V.

First I want to know if this feature can be disabled by any means.

If it cannot be done, I want to know if I can lower the VPWR voltage to 24V by Zener diode or a regulator and then rely on the charge pump to deliver the necessarily high gate voltage to turn on the MOSFETs.

I am using logic level VGS MOSFETs for this design so it should not be difficult to turn on. Will this modification causes other issues? (OVDS or the internal zener diode clamp I guess?)

Your suggestions is much appreciated.

Thank you.

Eric

  • Hi Eric,

    Thanks for reaching out!

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    Regarding VPWR, we specify that 40V is an absolute maximum.  We recommend a maximum supply voltage of 24V; so you should not be supplying the VPWR pin with more than 24V...  The reason for this protection is so that the internal charge pump among other internal circuits do not get damaged.

    This feature cannot be disabled; only reset with a high-to-low transition of CS, assuming the fault has been fixed.

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    You can create a Zener diode regulator to try and supply the driver; but you will need to make sure you supply enough current to both the Zener to regulate, and to the driver to operate as intended.

    I would also look into an LDO or see if you have another power rail available to you, between 8V and 24V.

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    Thanks,

    Aaron Grgurich

  • Hi Aaron,

    Thank you for your reply. Please allow me to clarify my idea a little bit.

    In the datasheet, it has specified the VPWR should be connected to the drain of the MOSFETs.

    As the OVLO is limited to only 27.5V. I am considering to lower the VPWR by external regulator or by a zener diode. In this way, the drain of the MOSFETs will no longer be limited by the OVLO and VPWR limit.

    However, I am concerned with the following:

    1. the VGS will still be sufficiently high to fully turn the MOSFETs on if VPWR and the drain are not at the same potential.
    2. other issues that may arise when these two are not at the same potential.

    Thank you.

    Eric

  • Hi Eric,

    Thanks for the additional details!

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    You may be able to do the following, but it comes with some compromises:

    • Keep the MOSFET(s) connected to the +30V rail
    • You can give the driver a lower V(PWR) voltage by using any of the following:
      • Zener
      • LDO
      • Or a separate existing power rail.

    The Compromise:  By doing this, you will basically be going around the "OVDS" protection.  If you are okay without that protection, then you should be able to proceed.

    Regarding your V_GS concern, I agree this is an important consideration!  Looking at the "Electrical Characteristics" table on page 6 (please see image below), this should give peace-of-mind.  If you give V(PWR) 24V, then you will get the maximum charge pump voltage of 40V.  For additional information on the charge pump, please look at the "Charge Pump Operation" section on page 14.

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    I hope this helps clarify things and answers your questions!  If you have additional questions, please feel free to follow up.

    Thanks,

    Aaron Grgurich

  • One last point, be sure to keep the two bypass capacitors on the V(PWR) pin.  (and physically very close to the pin too).

    Thanks,

    Aaron

  • Hi Aaron,

    Thanks for pointing out the VCP range. I am aware of it but I am however, more concerned about the Gate drive voltage two lines below.

    I suppose the VG in here means the gate voltage to the chip GND. If it is true, then the VGS would be below the VGS needed to turn on the MOSFET when VDRAIN is 32V and VPWR is at 24V. A clarification in here would be much appreciated.

    Best,

    Eric

  • Hi Eric,

    What is your required V_GS to turn on the MOSFET?

    Yes, "V_G" is with respect to GND.

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    If you provide V_PWR with 24V, there should be approximately 40V on the output of the gate driver.  The "V_G" specification you are referencing is simply showing the range of voltages that the gate driver would push out, with respect to a range of V(PWR), ranging from 8V to 24V.

    The charge pump voltage, V(CP) will be the same as V_G, because it is the supply for the high-side driver.

    Please reference the "charge pump" section below:

    -------

    So, if you give V(PWR) 24V, then you should get a charge pump voltage of around 40V.

    -------

    I hope this helps!

    Thanks,

    Aaron Grgurich

  • Hi Aaron,

    Thank you for your clarification.

    The MOSFET I chose has a VGS(th) of 1-3V. In order to reach a reasonably low RDS(ON), it will need to have a VGS of 4V at least. 

    Indeed the two parameters in the TPIC44H01 datasheet is a bit misleading. I presume the actual meaning in the "VG" row actually means the Gate voltage can range from VS + 4 to VS+18V?

    Best,

    Eric

  • Hi Eric,

    You are welcome, and thanks for the additional information!

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    Yes, what the "V_G" spec is trying to say is that given a range of V(PWR) from 8V to 24V, the gate drive voltage (which comes from V(CP)) will range from V(PWR)+4V to V(PWR)+18V.

    So, if you supply V(PWR) with 8V, you should see approximately V(PWR)+4V, and if you give V(PWR) 24V, you should see approximately V(PWR)+18V.

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    So, if your bus voltage is 32V, and your gate voltage will be around 40V, you should be in the clear.  Assuming that your drain and source voltage will be the same voltage when the external FET is on, your V_GS would be 8V, which will be plenty (based on the specs you just gave me).

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    I hope this clears things up for you!
    Thanks,

    Aaron Grgurich