TPS7A94: Output Capacitor ESR

Hello Srikanth,

Thank you for the quick response.  I am wondering about the max ESR in the case of using a Tantalum capacitor on the output.  

Thanks,

Jon

Hello John,

                 What is the value of the Tantalum capacitor you wish to use at the Output pin? 

Regards,

Srikanth

Hi Srikanth,

I don't have a specific value picked out but likely to get a low ESR value it would probably end up be being around the 100 uF range in a large package.

Regards,

Jon

Hi John,

             I will get back to you within 2-3 business days with the ESR value. If such a large C_OUT is being used, please be sure to use a SS cap to limit the inrush current at start-up. Thanks!

Regards,

Srikanth 

Hi John,

             We strongly recommend that a ceramic capacitor be used as C_OUT. However, if a Tantalum Cap has to be used, could you provide us the value/range of V_IN, V_OUT, I_LOAD, Ambient operating temperature and the value & model # of the tantalum C_OUT you wish to use? This will help us setup the Simulation environment and verify the part stability. Apologies, but this could take us up to a week to verify. Thanks!

Regards,

Srikanth  

HI Srikanth,

The Vin=3.75V

Vout=3.3V

ILoad = 600 mA

The proposed Tantalun Cap is F381A106MMA from AVX which is a 10 uF capacitor.  I am open to using two in parallel to lower the ESR.

Temp conditions considered up to 105C.

Regards,

Jon

Hi John,

             Thank you for the test conditions. I'll try to get back to you by the end of next week. Thanks!

Regards,

Srikanth 

Hi John,

             Will you using a Bypass capacitor for the load and/or a ferrite bead? If so, could you please provide details of these components as well? Thanks!

Regards,

Srikanth

Hi Srikanth,

Sure, there will be no ferrite beads.  There will be approximately 10 uF of ceramic bypass capacitors on the load in after the LDO.  This is in addition to the LDO output capacitor.

Jon

Thank You!

Regards,

Srikanth

Srikanth,

Thank you for the support.

Jon