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UC1843A-EP: UC1843A-SP Oscillator frequency bend and temp. effect

Part Number: UC1843A-SP
Other Parts Discussed in Thread: UC1844A,


I'm planning to drive my FET with 300kHz switching frequency and %50 max. duty cycle. Therefore, I'll try to set the internal oscillator to 600kHz.

However, when I arrange it according to below curve at datasheet. I saw that I'll work where a band occurs at my operating region.

I'm concerned about to work around band. The temperature effects and aging may effect my swithing frequency.

Is it safe to work around that point considering IC operating temperature range for long life design?

Is there possible any draft at oscillator frequency because of working that band in long term?

Please, comment on my concern.

  • Hi, 

    There is a mistake in your design, RT is recommended to be large than 5kohm.

    If you want to limit the maximum duty at 50%, UC1844A is recommended.



  • Hi, 

    Thank you for your correction. It is good to hear this answer at preliminary design phase.

    I saw some clue about not to use Rt lower than 5kohm at datasheet. However, there is no direct restriction about it.

    There is some clue that Rt should be >5kohm at figure 16 and figure 17 of datasheet.

    However, I also cannot understand the dead time issue. This is a single drive output IC and I think there will be no dead time issue.

    1) Could you please show how a user can understand that Rt shall (as a restricition for proper operation) be higher than 5kohm?

    2) Could you please inform that why there is dead time issue for this IC (UC1843A-SP)? There is no shoot through configuration of FETs because of single pwm output.

    3) The purpose that I want to use UC1843A-SP that I don't want to restrict my self. I think that %0-%80 duty cycle configuration can perform better dynamic performance than %0-%50 duty cycle configuration. Could you please confirm?

    Best regards

  • Hi, 

    1) if Rt is too small, means large Ct and large charging current, then a minimum deadtime is required to discharge Ct, at the same time, resister Rt is also still trying to charge Ct. so a too small resister will limit high frequency.

    2)  larger Ct, larger dead time, and smaller Rt. will cause the issue as mentioned in 1), TI don't recommend a dead time larger than 15%.

    3)  I don't think so, the maximum duty cycle is determined by your design, and keep enough duty margin between normal working duty and maximum duty.

  • Hi,

    Thank you.

    We don't understand the "dead time larger than %15". Which of %15 is unknown.

    Please, explain further with an example calculation for this issue.

    TI recommends to choose Rt higher than 5k. However, we need 300khz. Therefore, we will choose Rt=5k and Ct=1nF to obtain 300kHz.

    Is it safe to work at this limit conditions considering long term life usage of the device? Because, 1nF is miminum value at figure 16.

  • Hi, 

    15% period.   the fosc is around 300kHz, the PWM switching frequency fs is half of fosc.

    May I know 300 kHz is fs or fosc?    fosc should be set below 500kHz.   

    the fosc of UCCx8C4x can be up to 1 MHz