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CSD19536KTT: TIDA 010030

Part Number: CSD19536KTT

Why Q30 272Amps is used for 30A BMS design? And what is the use of C68 and C69?

  • Hello Rajib,

    Thanks for your interest in TI FETs. The maximum continuous current published in the datasheet is a calculated quantity assuming Tcase = 25°C & Tj = Tjmax = 175°C. For more details, please see the link below to a blog explaining maximum continuous current specs in TI datasheets.

    Holding Tcase = 25°C would require an "infinite" heatsink to dissipate the heat. In the real application, the current thru the FETs is limited by the maximum power dissipation which keeps Tj < Tjmax (+ margin). This reference design is using 3 x devices in parallel for the charge/discharge FETs to reduce conduction (I2R) loss and spread the heat to multiple packages in over a larger surface area to cool the FETs. For 3 parallel FETs conducting 30A (10A each), the I2R loss at Tj = 150°C is about 0.5W per FET. The D2PAK is capable of about 4W maximum power dissipation depending on the PCB and ambient conditions.

    The CSD19536KTT is our lowest on resistance/highest cost 100V FET in D2PAK. We may have more cost effective FETs in the same or smaller (5x6mm SON) packages depending on your requirements. The second link is to a TI FET selector for load switch applications. Just remember to divide the current by the number of FETs in parallel.

    I am going to forward this to the BMS applications team to answer your question regarding the capacitors.

    https://e2e.ti.com/blogs_/b/powerhouse/posts/understanding-mosfet-data-sheets-part-3

    https://www.ti.com/tool/LOAD-SWITCH-FET-LOSS-CALC

    Best Regards,

    John Wallace

  • Hi Rajib,

    The capacitors are for ESD protection. This application report explains the use of caps between BAT+ and PACK+ more: https://www.ti.com/lit/an/slua368/slua368.pdf 

    Many systems use 2 capacitors for redundancy in case one capacitor is shorted, the other will prevent BAT+ and PACK+ from shorting.

    Best regards,

    Matt