Are there any drawbacks or concerns using by the TPS7A4701 in following configuration:
Setting the output voltage (via resistors at feedback pin) at a setpoint that is greater than the input voltage?
The nominal condition would be Vin<Vout_setpoint and I would expect the internal FET to be fully saturated, therefore Vout≈Vin-Vdropout. For this application the customer is wanting the LDO to nominally pass the input voltage (like a load switch) but limit the output voltage when Vin>Vout_setpoint. could this work as long as the Vin is below the abs max ratings?