UCC28780: 5V, 10A design using UCC28780

Hello Ankit, 

Thank you for your interest in the UCC28780 active-clamp flyback controller. 

Data in the User Guides for the GaN EVM and the Si-based EVM show that > 92% average efficiency is achieved for a 45-W design operating at 115Vrms, however the output voltage is at 20V.  It will be more difficult to achieve 92% for a low-voltage, higher-current output such as your requirements. The controller by itself cannot deliver any specific efficiency, but its operation helps facilitate lower losses with the proper selection of active and passive components. 

There are two simulation models, one for GaN-based design and one for Si-MOSFET design. These are Simplis models and will not work in SIMetrix.  
We are not in a position to generate a custom model to your specifications.  
I recommend to go through the UCC28780 Excel Design Calculator tool (https://www.ti.com/lit/zip/sluc664 ) from beginning to end and make sure that each of the user entries conform to your choices and selections. Several parameters depend on other parameters, so if you made a first pass, then made some changes and forgot to go back and adjust any parameters that were dependent on the changed values, that may result in improper behavior.  One example is the RDM resistor, whose value depends on 3 other resistors, a turns-ratio, and the magnetizing inductance.  Changing any one of those parameters requires recalculating Rrdm. 

Regards,
Ulrich

Hello Ankit, 

I am a little confused by the TIDA-010047 USB-PD design brought into the picture.  It's parameters are not appropriate for a single-output 50W design.

To be clear, in my opinion, I believe it is possible to exceed 92% efficiency with an ACF circuit (with UCC28780) at full load of 5V, 10A at input voltage of 115Vrms.  This applies to a single, fixed output voltage, not as a subset of a variable-output USB-PD type design. 

All of my comments and recommendations are based on that assumption of 100~130Vrms input (not 90Vrms, 85Vrms?) and fixed 5V output, 10A maximum.
Please confirm this assumption. 

Assuming so, the UCC28780EVM-021 is the proper circuit arrangement example to follow.  That transformer's turns ratio is appropriate for fixed 20V output.  Simple iteration of the ratios reported in the User Guide result in actual turns of Np=21 : Ns=4 : Na = 3 : Nsa = 2.  The Nsa winding is a secondary-side auxiliary bias for the SR controller.  This results in a reflected voltage of 20V/4T *21T = 105V.  

For a 5V output, you'll need about a turns ratio of 21:1 to get the same reflected voltage.  The existing core size is a low-profile RM8/ILP, and probably can be "stretched" to handle 50W (11% power throughput increase) without increasing the primary turns.  But if the losses go up too much, you may have to resort to a normal-sized RM8 core to fit more primary turns and thicker wire.  (Or, a different core shape of suitable Ae and Ve).

For 5V output reflected to the primary-AUX, you'll need ~15V, or 3:1, and for an SR bias, you'll need about 10V or 2:1.
This results in a 21 : 1 : 3 : 2 turns-ratio for Np : Ns : Na : Nsa.  The single-turn secondary will likely consist of multi-filar wire.  Primary and secondary windings should definitely be Litz wire.  I'm not sure that a 1-turn foil winding would be practicable.  The 2 Aux windings can be solid wire, but multi-stranded for better coupling. 

Because of the turn-ratio change and higher current, your secondary resonance caps and output cap need to increase in value.  The primary MOSFETs might stay the same, or you may choose a slightly larger bottom FET due to the higher current.  The top Fet can be smaller (higher Rds(on) since the clamp current is lower, so it helps reduce total switched node capacitance.  400-V Fets can be used.

Please use the Excel tool to work through the choices and derive the appropriate resistances for the controller. 

For your SR simulation, I suggest to download the UCC24612-2 SR controller model ( https://www.ti.com/lit/zip/slum597 ).  At 130Vrms max input, the secondary reflected voltage is about 9V, so a 30 or 40-V MOSFET can be used with plenty of margin available for leakage inductance spikes. 
By ratio of current squared, the 16mR FET for 20V turns into 16 *(2.25/10)^2 = 0.81mR to keep the same conduction loss.  
CSD18510Q5B ( https://www.ti.com/lit/gpn/csd18510q5b ) is a 40-V, 0.96mR FET from TI. 
CSD17570Q5B ( https://www.ti.com/lit/gpn/csd17570q5b ) is a 30-V, 0.92mR FET from TI.
CSD16570Q5B ( https://www.ti.com/lit/gpn/csd16570q5b ) is a 25-V, 0.82mR FET, but may not have enough voltage margin. 
If necessary, two smaller FETs (higher -R) may need to be paralleled to reduce R further. 

Alternatively, the "SBD" part in the SIMPLIS model (Schottky Barrier Diode) may be redefined to have ~1.2mR forward resistance (to partially account for Rds(on) rise with temperature) and 0.1mV forward voltage just to have a number in the parameter box. Its output capacitance should be increased to match that of the MOSFET intended to be used, because this capacitance is included in the total switched-node capacitance.  

The input EMI filter and rectifier and bulk cap may need to be modified to accommodate the higher power.  
Several design iterations will be necessary to optimize everything.

Regards,

Ulrich

Hello Ankit, 

After making corrections to a local copy of the calculator file you provided, it recommends RDM = 85.5kR and RTZ = 437.7kR.

The closest standard 1% values are 86.6kR and 432kR, respectively. 

We're working to release an upgraded tool as soon as we can.

Regards,
Ulrich

Hello Ankit,

I cannot deduce what is causing the simulation output to fall to 0V from the information provided.  16W is about 30% of 50W, so the operation should be somewhere in the lower ABM count; say 2, 3, or 4 pulses per burst, I'm guessing.

0V on the output means switching has stopped and we need to determine the reason for switching to stop in this line and load condition. It could be any of the various faults has happened that results in a shutdown. Check if VDD of the UCC28780 has fallen below the UVLO threshold.  Check if Vout has risen to the OVP threshold, or if peak primary currents exceed the OCP threshold. 

I don't know what is going on in the simulation, but I suggest to set the load level to a point where regulation still works (like 17W?) and examine the waveforms of every signal that has a protection threshold to see how close it is getting to possibly triggering that protection.  Then carefully reduce the load in small increments while monitoring the likeliest signals with respect to their protection thresholds to see which one may be getting even closer. 
Eventually, you will reach the point where the shutdown occurs and you can identify which signal caused it.  Then figure out why that signal was moving toward the protection level and whether it is expected behavior or unexpected behavior. Then you can figure out what to do about it.
The main focus is to isolate what exactly is causing the shutdown by using the process of elimination.

I'm not sure when the revised calculation tool can be released.  I'll check on its status. 

Regards,
Ulrich    

Hello Ankit,

Thank you for the additional information.  I am certain the output is shutting down because of over-voltage protection as Vout rises above 6V. 

From the symptoms you describe (regulating at loads > 50%, and Vout rising as load gets lighter than that) I believe that the feedback loop is running into some sort of clamped operation. More specifically, I think the shunt regulator is saturating at its lowest voltage and cannot drop lower so it is unable to increase the current into the opto-coupler. Higher FB current would allow the controller to change modes from AAM to ABM and further to accommodate lighter loads.  If the FB current cannot increase, the controller becomes "stuck" at that operating point, even if the output load is reducing.  Therefore Vout has no alternative but to increase.  Fortunately the OVP function detects the OV and shuts down the operation.

As load gets lighter, Vout rises incrementally and the shunt regulator (such as ATL431) drives feedback current through the opto-diode by lowering its cathode voltage.  The opto-diode current is derived by the voltage established across "Rbias1" from Vout to the anode of the opto-diode.  Since the cathode of the diode is connected to the cathode of the shunt, as the shunt voltage drops, so follows the diode voltage drop, which increases the V-drop across Rbias1.

If the shunt voltage "bottoms out" (cannot decrease further) then the current through Rbias1 cannot increase further, hence the feedback loop becomes stuck at that operating point.  This situation may happen if you take a reference design which had a 20-V output and modified it to produce a 5-V output, but forget to adjust the values of Rbias1 and Rbias2 appropriately for the 5-V level.  Depending on how it is connected, Rbias2 may or may not need to change value.  But in any case, Rbias1 does need to be reduced when changing from 20V to 5V output.

With 20V output, the shunt's cathode voltage can range near 20V down to 2V, so Rbias1 would have a relatively high value.  With a 5V output, the shunt's cathode voltage can only range from 5V down to 2V (from 6V actually, accounting for the OV), so Rbias1 must have a relatively low value to generate the same range of feedback control current.  Other factors in the simulation can also be involved with the limiting current, such as how the opto-diode drop is modeled and what value of CTR is used at the operating point. 

I think this shutdown issue will go away if you use about 1K for Rbias1.  The you should be able to simulate to "no-load" conditions.  

Regards,
Ulrich

Hi Ankit,  

Having received and run your simulation file (as modified from the original UCC28780 SIMPLIS file), I've found two main issues: that the output cap still had 20V as its initial condition, and the VS-pin resistor-divider set the VS signal too close to the over-voltage threshold of 4.5V (typ).  
Changing Cout IC=5V eliminated the long dead times between short bursts while the voltage loop was recovering from saturation.
Reducing Rvs2 value by ~10% raises the OVP threshold so switching does not stop while the loop settles. 

I also reviewed the Excel Calculator Tool that you provided and made some changes that I thought would better fit your application.  
In particular, your response requirement of 0.2V deviation for 50% load step points to a large Cout.  From your email:
"As load change requirement is from 100% to 50% (Not 0% to 100%), so my plan for C02 is to use ... 150uf x 5  (Total = 750uF, Effective ESR = ~3 mohm)." 
I think 750uF may not be enough capacitance to support a 0.2V maximum deviation in Vout. 

The datasheet equation (38) is valid for most usual conditions.  The Excel tool equation accounts for ESR drop as well, but is specifically targeted for 100% load steps and will overstate Cout value for your application.  Furthermore, your comment of "...100% to 50%..." load change indicates that a step-down direction is more important that a step-up load change.  I'd like for your to verify what is more important, what is equally important, and what is less important to accommodate for your application.  These will help inform the strategy for your design.   

In most TL431 + optocoupler feedback loops, the optocoupler response is the "bottleneck" in the loop response, and generally is slower when turning off.  When the system goes from light load to heavy load, the TL431 cuts off the opto-diode current, but the output transistor still conducts as the base electrons recombine with holes during the storage time and eventually the collector current drops to zero.  This means that Cout is holding up Vout until the FB current gets low enough for the controller to command enough output current to stop and reverse the droop in Vout.  
Conversely, when the system goes from heavy load to light load, there is little FB current and the TL431 acts to rapidly increase the opto-coupler current. Since there is no storage time to wait for, this direction is much faster than the other and the control can cut off power to the output sooner.  So Vout overshoot is usually lower than Vout undershoot for equal-magnitude but opposite-polarity load steps.  

Assuming (and this assumption must be verified or refuted) that going from 10A to 5A load is the more important transient direction, the 5A change in current through the ESR accounts for ~15mV of the 200mV allowable transient, leaving 185mV for Cout to absorb while the feedback loop cuts back on power transfer.  In my experience, the typical loop response time is about 100us in the un-load direction, so Cout should be > 5A*100us/.185V = 2700uF.  
Part of this assumption is that the un-load step is immediate, not gradual.  

Another part of the assumption is that the other way, 50% load to 100% load, is less important; either more than 0.2V droop is allowable, or the di/dt of the 5-A step is slow enough to avoid a deep droop.  If this is not the case, then Cout must be reevaluated and may be higher than 2700uF.  
Please check the di/dt of your load changes, up and down, to verify or modify the Cout calculations to meet your 0.2V transient spec, or re-evaluate the 0.2V target. 

Another item from your email: "Now, for Feedback TL431, I will be referring the excel sheet but I see larger Cdiif and Cint capacitor value in comparison to TIDA-010047 (works for 5V design as well) and UCC28780-021 eval kit schematic, I don’t know the reason but if you have any thoughts, please advise." 

In both of these designs, the output currents are lower, the output voltages are higher, and they both use ATL431 to help minimize no-load standby input power.  With UCC28780, Cdiff is used to bypass ripple voltage around Rbias1 which is used for ABM control.  For your design, Cdiff is much higher because Rbias1 is much lower because TL431 needs higher bias current than ATL431 and your Vout is lower.      
Cint is higher because Rvo1 is lower when using the TL431, to minimize TL431 Iref bias current influence on Vout setting. 

Cdiff and Cint will usually be different from one design to another, but the main reason their values are so much higher in your design compared to the TIDA and EVM designs is that the resistor values they interact with are much lower due to the higher TL431 currents involved with regulation. 
Another assumption to test is that no-load standby power is not an important consideration to your design. 
If it actually is important, maybe consider using the ATL431 regulator instead. 

Regards,
Ulrich