UCD9090-Q1: output enable

Delaney Berger

Part Number: UCD9090-Q1
Other Parts Discussed in Thread: UCD9090, TPS38700

Hi Team,

Can you checknmy understanding?

For all GPIO configured as an output enable, is that a timing UCD9090 float before UCD9090 reset? Should we add the weak pull low?

Thank you,
Delaney

0 yihe over 2 years ago

Not all IOS are default at Hi-Z.

if customers have concerns about Hi-Z . A weak pull down is ok

Regards

Yihe

0 Delaney Berger over 2 years ago in reply to yihe

Hi Yihe,

I have another questions about the dependency between sequencer and voltage monitoring:

sequence by TON delay
Sequence by the power good of N-1 rail, for example, EN2=1 if rail 1 power good=1. Here we can also mitigate TON delay

If number one is OK, I do not worry about the ordering of each power rail?

Also, how about the correlation between margin pins and monitoring pins to complete the closed-loop margining?

Lastly, do you have recommendation for any discrete margin control IC? I see the TPS38700 (VRS10 power sequencer) and TPS38900601 (VRS12 monitoring).

Thank you,

Delaney

0 yihe over 2 years ago in reply to Delaney Berger

Please refer this quick to understand for the sequencing.

For the margining and monitoring, the margining will not start until the followings are met:

1. the rail reaches its POWER_GOOD threshold

2. customer issue the margining enable to start the margining.

I am not sure there is a dedicated IC to support margining

Regards

Yihe

0 Delaney Berger over 2 years ago in reply to yihe

Hi Yihe,

Thank you!

Best,

Delaney

Power management forum