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TPSM8A28:Conditions for applying external voltage to Vcc pin

user1160324
Prodigy 50 points
Part Number: TPSM8A28

Vin端子に3.3V±5%を印加した場合、Vcc端子に外部電圧を印加する必要がありますか?

  • 0
    TI__Genius 14777 points

    Hi,

    Could you pls use English to describe your question? Thanks.

  • 0
    TI__Genius 16660 points

    I translated your question as the following. 

    "If 3.3V ± 5% is applied to the Vin terminal, is it necessary to apply an external voltage to the Vcc terminal?"

    No, but to get the full load current, adding the external bias may be necessary. 

    See section 7.3.1 https://www.ti.com/lit/ds/symlink/tpsm8a29.pdf#page=11

    If the input is only 3.3V and never above 5.5V,  consider connecting VCC and VIN together it may be beneficial. 

    The following link is data taken at 3.3V input voltage for a lower current rating IC (not the TPSM8A28).   The TPSM8A28 uses the higher current version of the IC. 

    https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1006339/faq-tps548a28-efficiency-output-voltage-for-3-3v-input-voltage?tisearch=e2e-sitesearch&keymatch=TPS548A28

  • 0 in reply to David_Daniels
    Prodigy 50 points

    Thank you for your response.
    I have an additional question.
    When 3.3V±5% is applied to the Vin terminal and 1.0V-10A is output, is it necessary to apply voltage to the Vcc terminal?
    What is the method of handling the Vcc pin when voltage application to the Vcc pin is not required? (e.g., terminated with 1uF)
    If voltage must be applied to the Vcc pin, is it sufficient to simply connect it directly to the Vin pin (3.3V±5%)?
    What are the conditions under which 4.5V to 5.3V must be applied to the Vcc pin?

  • 0 in reply to user1160324
    TI__Genius 16660 points

    When 3.3V±5% is applied to the Vin terminal and 1.0V-10A is output, is it necessary to apply voltage to the Vcc terminal?

    No, it is not necessary. But the VCC voltage will be slightly lower and VCC is the gate drive voltage  and the on resistance of the power stage fets are higher.

    The VCC LDO is operating in dropout, since the LDO is set up to regulate to 4.5V and the input voltage is lower than 4.5V.   The VCC will be slightly lower than the VIN voltage and the on resistance higher which affects efficiency.

    What is the method of handling the Vcc pin when voltage application to the Vcc pin is not required?

    The VCC has an internal 1uF capacitor, leave open when operating at input voltages greater than 5.5V.

    When operating at input voltages < 5.5V connect the VCC to VIN, to give the best efficiency.

    https://www.ti.com/lit/ds/symlink/tps548a28.pdf#page=32 figure 8-3 shows the efficiency improvement when using the external bias on an VCC pin. 

     

    What are the conditions under which 4.5V to 5.3V must be applied to the Vcc pin?

    I do not know of any conditions that require an external bias to be applied.  Using the external bias lower the on resistance which improves efficiency.

    the improvement in efficiency may extend the ambient temperature or load current that the device can operate