Hi team,
Because PG-pin is open-drain, the following output appears after an external pull-up according to 7.3.3 Power Good.
1. When the output voltage is larger than 90% to the target value, the PG-pin become High.
2. When the output voltage is less than 85% to the target value, the PG-pin become Low.
However, according to 7.2 Functional Block Diagram, when the VFB is larger than V_THPG, it appears that the FET on the front of the PG-pin is on. This mean that PG-pin goes low when the output voltage is larger than 90%. (In the block diagram, the logic of ① and ② above appears to be inverted.)
I think the description of 7.3.3 Power Good is correct. Is this correct? And how should we understand the block diagram?
Regards,
Noriyuki Takahashi
