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# CSD13381F4: offset issue

Part Number: CSD13381F4
Other Parts Discussed in Thread: TINA-TI

Hi Sir,

my we learn from you,

Refer to the following NMOS circuit diagram, input a square wave to the Drain terminal (point C1), and pull low from 3.3V==>0.1V, 3.3V==>0.2V, 3.3V==>0.3V, all the way to 3.3V==>1V

At the same time, looking at the change at the Source terminal (point C2), it can be seen from the figure that when the point C1 is 3.3V==>0.7V, there will be a relatively obvious offset voltage difference at point C2 (compared with the voltage at point C1)

What is this phenomenon? How to explain that there is an offset voltage difference, thank you for your help.

• Hello Tommy,

Thanks for the inquiry. I ran a TINA-TI simulation (attached). Normally, when the drain voltage goes to 0V, VGS = 1.8V, the FET is on and VDS ~ 0V. As the low level increases, this voltage is subtracted from VGS. At 0.1V, VGS = 1.8V - 0.1V = 1.7V. You can see the offset at each step is increasing. Eventually, when the low level is around 0.7V and VGS should be 1.1V, the drop across VDS starts increasing as it approaches the threshold voltage because the FET is not fully on and the channel can no longer support the drain current. The offset will be even greater if there is any load current thru the FET. I'm not sure what the purpose of this test is. However, if the CSD13381F4 is being used as a high side load switch as shown in your schematic, the gate must be pulled higher than the drain by at least 1.8V to guarantee on resistance of the FET. Let me know if you have any questions.

Best Regards,

John Wallace

TI FET Applications

CSD13381F4_switch.TSC