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UCC5870-Q1: GM fault

Part Number: UCC5870-Q1

Dear team,

1. Could you please tell me our device how to monitor gate voltage? We found that when we disconnected the resistor Rgon between OUTH and Gate, our device will report GM fault.

2. Can our device support 900V bus voltage? The background is that our device can work normally under 500V with inductive load, but when the bus voltage increased to 900V. Our device will report GM fault.

3. When we test one device, nFLT1 pin is puled low. We read the status registers, STATUS3[GM_FAULT] =1 and STATUS2[OR_NFLT1_PRI]=1, no other fault. But we set CFG9[GM_FAULT_P]=0, and readback is also 0. So GM fault won't pull low the nFLT signal. But there is no other fault, we don't know why the nFLT is pulled low.

Thanks & Best Regards,

Sherry

  • Hi Sherry,

    Thanks for your post!

    1. Could you please tell me our device how to monitor gate voltage? We found that when we disconnected the resistor Rgon between OUTH and Gate, our device will report GM fault.

    You can find the detailed description of GM fault in Section 7.3.5.13 of the datasheet. The behavior you described is exactly what this feature can be used for! It is comprised of 2 checks: First it will monitor the communication across the isolation barrier from input-to-output then that state is communicated back to the primary side and compared to ensure input and output matches. Secondly, it will monitor the actual gate voltage and converted to a logic signal to compare with the actual input voltage. When there is no gate resistor present, this means the output is open (there is no load for the output to charge up to the gate voltage) and thus the gate driver output does not match the input.

    2. Can our device support 900V bus voltage? The background is that our device can work normally under 500V with inductive load, but when the bus voltage increased to 900V. Our device will report GM fault.

    Based on the creepage/clearance of the package, which is 8mm, and the isolation capability of our capacitive isolation technology, then yes this device is able to meet 800V (under basic isolation standards). I suspect the higher bus voltage can result in higher dv/dt, which can be beyond our specification of 100V/ns, or higher dv/dt can also result in coupling from secondary-to-primary side and could be adding noise to the inputs (which is a part of GM fault checking). If noise is observed on the inputs, then you could add higher filtering capacitance.

    3. When we test one device, nFLT1 pin is puled low. We read the status registers, STATUS3[GM_FAULT] =1 and STATUS2[OR_NFLT1_PRI]=1, no other fault. But we set CFG9[GM_FAULT_P]=0, and readback is also 0. So GM fault won't pull low the nFLT signal. But there is no other fault, we don't know why the nFLT is pulled low.

    Please double-check the faults in Table 7-1. Fault and Warning Operating Modes (default) of the datasheet. Maybe there are some default FAULTs that have been overlooked and may still cause FLT1 to pull low. Please ensure they have checked all 5 of the STATUS registers.

    Regards,

    Audrey

  • Hi Audrey,

    Thanks for your detailed reply!

    Yes, I noticed Section 7.3.5.13 of the datasheet. I am still confused about the gate driver voltage monitoring. Firstly, our device need to monitor the actual gate voltage of the power transistor. In my understanding, our device monitors OUTH voltage as the gate voltage. If we disconnected the resistor Rgon between OUTH and Gate, the OUTH voltage still exist, so gate voltage is correct, right?

    Thanks & Best Regards,

    Sherry

  • Hi Sherry,

    Good question! Since we have 2 outputs, OUTH and OUTL, then it will see from two "angles". If the resistor tied to OUTH comes off, for example, the pullup gets disconnected from the gate, and if the resistor from OUTL comes off, the pulldown gets disconnected from the gate. There are two comparators you can see from Figure 7-31. These two comparators will work such that when the output should be low and OUTL is on, the gate check will be performed on OUTH (to see the actual gate voltage) through the OUTH resistor. So if the gate resistor is missing on either OUTH or OUTL, the check will catch it through the gate path.

    Hope that clears things up!

    Thanks,

    Audrey

  • Hi Andrey,

    Thanks for your clarify, but I still have some confusion.

    These two comparators will work such that when the output should be low and OUTL is on, the gate check will be performed on OUTH (to see the actual gate voltage) through the OUTH resistor.

    How to check the gate path? You mean to test the voltage across the OUTH resistor? Is there one internal current source in the gate path?

    Thanks & Best Regards,

    Sherry

  • Sherry,

    Please refer to image below from the datasheet. I drew the example when input is off, and if the resistor at OUTH is broken, then the gate fault check will be incorrect.

     

    Hope this clarifies your question!

    Thanks,

    Audrey

  • Hi,

    1. For GM fault, if the customer sets tGMBLK=4000ns, the first pulse width is only 3us followed by 2us dead time. Will this condition report GM fault?

    2.  During working, our device reports PWM_COMP_CHK fault. Based on this fault, my customer have below two questions,

    1) Do we have more detailed PWM_COMP_CHK fault description? What is the checking mechanism? For example, this error is reported when the VCC2 exceeds a threshold for a certain period of time, then what is the threshold value and glitch time?

    2) What is the relationship and difference between PWM_COMP_CHK fault and GM fault? Does one fault will result in another fault?

    Thanks & Best Regards,

    Sherry

  • Hi Sherry,

    Thanks for your questions. I have included responses below:

    For GM fault, if the customer sets tGMBLK=4000ns, the first pulse width is only 3us followed by 2us dead time. Will this condition report GM fault?

    No, this will not cause a GM fault. The GM fault checks if the gate matches the expected state after the blanking time. This blanking time is reset after each output transition.

    2.  During working, our device reports PWM_COMP_CHK fault. Based on this fault, my customer have below two questions,

    1) Do we have more detailed PWM_COMP_CHK fault description? What is the checking mechanism? For example, this error is reported when the VCC2 exceeds a threshold for a certain period of time, then what is the threshold value and glitch time?

    2) What is the relationship and difference between PWM_COMP_CHK fault and GM fault? Does one fault will result in another fault?

    1) The PWM_COMP_CHK fault is triggered if, at any point, the PWM value received across the isolation barrier does not match the value sent from the low voltage side. Once the secondary side of the driver receives a PWM value it sends it back to the primary side. This value is compared to the value that was just sent, and if they do not match the PWM_COMP_CHK_FAULT is triggered. This is a digital comparison. 

    2) The PWM_COMP_CHK_FAULT is meant to monitor the internal communication lane. If the this internal communication fails, the fault is triggered. the GM fault is meant to monitor the gate state, for example detecting if the gate is shorted to VEE. It is possible for both faults to trigger at the same time. 

    Please let us know if this answers the customer questions.

    Best regards,

    Daniel

  • Hi Daniel,

    Thanks for your detailed reply!

    Let me explain the background of above two questions. 

    1. For the PWM_COMP_CHK fault, the customer found that during low side FET is turning on, the high side FET's gate pin will appear an unexpected spike pulse due to the miller effect, and then some high side FET drivers will report PWM_COMP_CHK fault while others not. They found that these drivers that report faults have a higher spike pulse voltage on Gate pin, so the customer wants to know the threshold and glitch time about the PWM_COMP_CHK function, then they can avoid such fault triggers. For example, if the spike exceeds 3V for 250ns, this fault will be reported.

    Question 1: What is the threshold and glitch time?

    Question 2: Does this fault reuse the detection circuit of GM fault?

    2. For the GM fault, what is our recommendation for tGMBLK? We have four choices, and the customer think the step between two choices is a little large.

    My customer is wondering whether below conditions will appear.

    1) If tGMBLK is too small, for example, 1us, the Vgate haven't rise up to VCC2 yet, but GM circuit has begun to compare the gate voltage with input, so GM fault will be reported.

    2) If tGMBLK setting is middle, for example, 2.5us, it may be the turn-on process at the moment and the interference is very high, such as the miller effect causing the gate level to be undesired, causing the fault to be reported.

    Thanks & Best Regards,

    Sherry

  • Sherry,

    1. For the PWM_COMP_CHK fault, the customer found that during low side FET is turning on, the high side FET's gate pin will appear an unexpected spike pulse due to the miller effect, and then some high side FET drivers will report PWM_COMP_CHK fault while others not. They found that these drivers that report faults have a higher spike pulse voltage on Gate pin, so the customer wants to know the threshold and glitch time about the PWM_COMP_CHK function, then they can avoid such fault triggers. For example, if the spike exceeds 3V for 250ns, this fault will be reported.

    The PWM_COMP_CHK does not monitor the output state, it only monitors the internal PWM communication lane, making sure that the PWM state transmitted on the primary side matches the PWM state received on the output. Because of this changes on the output should not cause a PWM fault. There are two possibilities that may be causing this fault. The first is a PWM input frequency faster than 50kHz, even for just a few pulses. The second is noise coupling into the PWM lane either from the primary side, or secondary side. Does the layout of this design have good bypass capacitance on all voltage pins(VCC1, VCC2, Vreg1, Vreg2)? Is it possible that the PWM_COMP_CHK fault is caused by one of these reasons instead ot the miller effect induced spike described? Does the customer have example waveforms they can share?

    My customer is wondering whether below conditions will appear.

    1) If tGMBLK is too small, for example, 1us, the Vgate haven't rise up to VCC2 yet, but GM circuit has begun to compare the gate voltage with input, so GM fault will be reported.

    2) If tGMBLK setting is middle, for example, 2.5us, it may be the turn-on process at the moment and the interference is very high, such as the miller effect causing the gate level to be undesired, causing the fault to be reported.

    Both of these are possible, depending on the system and how long the customer expects it to take for the gate to fully turn on. This depends on gate charge, gate resistance, and other parameters. We would recommend that the customer choose a tGMBLK time such that they expect the gate to be fully turned on. From what you describe, it sounds like the longest blanking time, 4us, might be the best option for this customer if they have concerns with the middle two options.

    Regards,

    Daniel