TPS2662: FLT signal timing

Miroslav Mrdjan

Prodigy 140 points

Part Number: TPS2662

Hello,

FLT signal has some contradictory or maybe definition is not straightforward.

According to datasheet we have:

but on the same page we have

Page 8 on this link https://www.ti.com/lit/ds/symlink/tps2662.pdf?ts=1652348966664&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTPS2662%253FkeyMatch%253DTPS26624

As you can see on second picture, time for FLT to go down from UVLO is 6us but according to first pic it is 875us. Also diagrams in the datasheet are showing this higher delay.

Which one is true? Or at least, what is the explanation of this.

Best regards,
Miroslav

over 2 years ago

0 Rakesh over 2 years ago

TI__Guru** 103636 points

Hi Miroslav,

Thanks for reaching out!

These two are separate control paths at FLT/ as you see in the block diagram. SWEN/ comes from UVLO and PGOOD is derived from the GATE voltage internally.

Best Regards,

Rakesh

0 Miroslav Mrdjan over 2 years ago in reply to Rakesh

Prodigy 140 points

Thanx Rakesh. It is not described which path the current protection has. Also SWEN?

0 Rakesh over 2 years ago in reply to Miroslav Mrdjan

TI__Guru** 103636 points

Hi Miroslav,

For UVLO, OVP, thermal shutdown and reverse current faults the SWEN signal gets changed.

Best Regards,

Rakesh

0 Miroslav Mrdjan over 2 years ago in reply to Rakesh

Prodigy 140 points

Thanx again, and what is over-current impact on FLT?
Per block schematic there is no relation between overcurrent and FLT signal. And per graph in the datasheet it falls after ~1ms. We are using TPS26621 which do not have flip-flop.

0 Rakesh over 2 years ago in reply to Miroslav Mrdjan

TI__Guru** 103636 points

Hi Miroslav,

During overcurrent event, the GATE is regulated to limit the current. So, the GATE enhanced signal goes low which asserts FLT.

Best Regards,

Rakesh

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TPS2662: FLT signal timing