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LM25117: layout review

Fred Cheng
Expert 5850 points
Part Number: LM25117


Hi team,

do you recommend make an routing path between CSG pin and CSG and remove the vias on the CSG plane (bottom-right cornor) , instead of just connect to the multiple ground plane with vias?

that way we 'll have better PGND signal integrity,  but I also worry if I remove the vias, the thermal will be worse since there's only one path back to PGND now.

may I know your suggestion?

  • 0
    TI__Mastermind 34875 points

    Hi Fred,

    How many layers of this board?

    CS and CSG signal trace should be routed in parallel for accurate current sensing.

    The CSG plane you mentioned should be routed to CIN ground in shortest way, you place multi vias on CIN ground plane.

    LM25117 require multi vias on thermal pad, 

    The width of traces connected to HB, HO, LO and SW pin should be >12mil 

    B R
    Andy

  • 0 in reply to Andy Chen
    TI__Expert 5850 points

    Hi Andy,

    thanks for your reply

    let's  skip the Cin thing first,

    I was asking if I need to build a extra path from CSG plane to CSG pin,

    or just like right now connecting the CSG plane to the ground plane through vias and let the return current back to thermal pad's via? 

    the latter one seems to have dirty ground and  unexpected  IR drop for CSG pin.

    or can I do both?

  • 0 in reply to Fred Cheng
    TI__Mastermind 34875 points

    Hi Fred,

    There should be extra trace from CSG plane to CSG pin.

    The CSG pin should NOT be connected to LM25117 ground directly.

    Pls refer to LM25117 EVM layout design.

    B R

    Andy