• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 63 subscribers
  • Views 144 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC5870-Q1: ADC operation preconditions

Rafael Lindner
Prodigy 50 points
Part Number: UCC5870-Q1

Hello,

I am using the UCC5870-Q1 A/D converter with "Edge-Sampling-Mode" configuration.

I have to read some ADC data after the device enters the "Active" operation mode for several system checks before switching-on the driver output.

Unfortunately, the ADC seems to start operation only after togelling the PWM Input IN+  from low-to-high and high-to-low.

Is there any solution for getting the ADC into operation without toggeling the PWM Input?

Is this untypical ADC behaviour and the preconditions specified in the datasheet?

Thanks for your feedback in advance!

  • 0
    TI__Expert 4070 points

    Hello Rafael,

    Thank you for reaching out!

    Our expert on this device is currently out, and should get back to you sometime next week.

    Thank you for being patient.

    -Aaron

  • 0
    TI__Genius 13460 points

    Hi Rafael,

    For the UCC5870-Q1 ADC you are correct, the ADC needs to receive 2 PWM input pulses to begin sampling. If you need to initialize the ADC sampling without toggling the output a solution would be to use the secondary side ASC. This implementation allows the ADC to receive the 2 necessary PWN input pulse while using the secondary side ASC feature to keep the output low.

    There’s 2 ways secondary side ASC can be achieved:

    1. Digital isolator to control AI5(ASC_EN) and AI6(ASC) pins
    2. Enable AI5 internal current source using SPI (AI6 should be shorted to GND2)
      1. Steps to achieve this:
        1. Program AI5 and AI6 for ASC and enable AI5 internal current source
          1. This is done in configuration 2 mode
        2. Go from configuration 2 mode to active mode(Output will be held low by secondary side ASC)
          1. When gate driver transitions to the active mode the internal current source will bias an external resistor to pull AI5 high(Secondary side ASC enabled). With AI6 shorted to GND2 the output safe state will be LOW
        3. With the output being kept low by secondary side ASC give the necessary IN+ input PWM pulses to initiate the ADC
        4. Disable AI5 current source
          1. Before beginning operation the gate driver must be taken back to configuration 2 mode to disable the current source (Disable secondary side ASC)
        5. Go back to active mode to begin gate driver operation

    Let me know if there's any questions.

    Best regards,

    Andy Robles