I'm trying to implement a dual active bridge controller with the UCD3138A64. I'm starting simple with a DPWM0 and 1 driving the primary side FETs with 50% duty cycle (a little less with dead time) and DPWM2 and 3 driving the secondary side FETs with 50% duty cycle and want to use the phase shift between 0/1 and 2/3 to control the power flow.
Unfortunately from what I have pieced together in the register guides, app notes and these help forums is the A64 version has removed the capability to set the PHASE_TRIGGER from a filter output. I'm trying to figure out if there is a work around to achieve this same effect in hardware with the available filter outputs.
I tried implementing an IRQ routine to have code check the front end error output and adjust the phase shift accordingly, but found that took ~3.4us. Does that seem reasonable? (I'm a HW eng not a FW eng so I don't have a good frame of reference, but that seems like a lot of clock cycles for a simple task. Maybe there is some much better optimization that can be done there?)
I'm using a 1MHz switching frequency and would ideally like my primary control loop operating at the same frequency. Even if the IRQ service time could be reduced to fit in this time, it still seems like it will use up way too much of the processor capability, so a solution in HW seems better. It appears most or all of the filter outputs are designed for controlling duty cycle rather than phase shift. Is there some way this could be adapted to achieve the phase shift I need? Something like use the filter to set a DPWMC duty cycle and use a DPWMC edge to create trigger the start of the secondary cycles?
