TPS62913: TPS62913 Regulator in place of TPS7A85 LDO and TPS546A24A buck regulator

Hello, 

Thanks for your question. Are these two separate designs, or is the DC/DC supplying the LDO?  All of these designs can be done either using the datasheet guidelines in Table 8-2, or by using the WEBENCH tool on the product page at www.ti.com\tps62913. To achieve the ripple you need, you may not need the ferrite bead filter, and that is an option in WEBENCH as well as by using the datasheet Table 8-3. Do you have transient requirements for these designs?

Hello Steve,

 As I mentioned, Yes separate designs.

1. One for LDO replacement- TPS7A85 with TPS62913

2. Another one for Buck regulator replacement- TPS546A24A with TPS62913

Not much but consider the transient requirements (20-50%). Please suggest.

Thank you Steve.

I have a query related to EN pin. It has internal pull-down of 500K (Weak). We are controlling the EN pin with controller( Sequence). In such cash do we need to keep external pull-down (1K/10K)?  

While doing the analysis on webbench, The o/p Voltage tolerance is 2.04% based on feedback resistor (ambient temperature 25 degree). But during 85 degree ambient the tolerance will more. Other than feedback resistor, can we control the tolerance like1%?

Any suggestion for above queries?

Hi

Steve will reply you tomorrow.

Shuai

If you are actively pulling down the EN pin with your sequencer, the pull-down can likely be removed. Can you share your design on WEBENCH? What tolerance of resistor are you using? The voltage reference of the TPS62913 is +/-1% from -40C to 125C.  The output voltage deviation is shown in the datasheet typical characteristics in Figures 6-51 through 6-53, using the 1% tolerance feedback resistors used on the EVM.  

1. The sequencer will pull-up the EN pin to turn-on the regulator, but it will depend the sequencing. Before that the regulator will be in off condition, So my query was the state of EN pin during off condition. Since this regulator has the internal pull-down, EN pin will logic low condition right, So do I need to keep external pull-down (1K/10K strong ) or not?

2. The tolerance of resistor is 1%.

Thank you for your feedback. We will closed it.

Hello Steve and Shuai,

I have a query related to related to Inductor selection w.r.t to duty cycle, frequency and output Voltage 3.3V@1-3A. (Input voltage is 5V with 5%tolerance).

In the datasheet it is mentioned to take take 2.2uF with the frequency should be 2.2MHz (Table 8.2)

8.2.2.2.2 Inductor Selection for the First L-C Filter:

 If Dmax is below 45% and the output voltage is above 2 V, use a 4.7-μH inductor to achieve the full output current or a 2.2-μH inductor for higher efficiency with a reduced maximum output current.

But in webbench simulation with 1MHz and duty cycle of 66.83% I am achieving the output.

Would you please suggest with 1MHz, 2.2uH the design is stable ? Can I go with this design?

Hello, 

The 5Vin to 3.3Vout is recommended to run at 2.2MHz, and you should use the 2.2uH inductor and not the 4.7uH inductor. If you use 1MHz, the design will be stable, but the phase margin will be low, which can be improved by adding a 100pF Cff in parallel with the top resistor in the resistor divider.  

Hello Steve,

Thanks for the suggestion. what about 12V input  and outputs like 0.88V, 1.2V, 1.8V and 5V. (the frequency 1MHz and inductor is 2.2uH) ?

Kapil, 

For 12V to 0.88V, 1.2V, and 1.8V @ 1 MHz, you can use the 2.2uH inductor as recommended in the table.  However, for the 5V output, I would recommend using 2.2MHz with the 2.2uH inductor as shown in the table 8-2 in the datasheet. 

Hi Steve,

Thanks for the clarification. I have one more query related to NR/SS pin. what is recommendation if the load is OCXO- 25MHz, 114MHz, and 10MHz and different voltage level. these rail are frequency sensitive (1.8V, 3.3V, 3.3V, 1.2V, 0.88, 0.8V).  So what is the value I should select. My requirement is (1ms-5ms). Can you suggest?

Kapil, 

The NR/SS cap is part of a filter on the bandgap, and larger values will provide more filtering as shown in the figures in the datasheet, specifically 6-29 through 6-44.  I would suggest using the largest cap that will still meet your startup time, such as a 470nF for a 5ms softstart time. 

Currently I have selected the 220nF (Sequence time 3ms max), and 470nF for OCXO-10MHz (3.3V@1.5A). Is it good? or should I go with 470nF for all the rails.

Hello Steve,

Thank you.

Hello Steve,

Thank you. I have few more queries related to parts that TI is Using in Application circuit and EVMs.

These components are the recommendation for switching frequency of 1MHz and 2.2MHz. If I see the graph of  Cin Capacitor (C2012X7S1E106K125AC) value w.r.t switching frequency in the TDK website, I value is not stable even for 1Mhz itself.

Same for output capacitor- 

Can you clarify on these points? Any suggestion or alternate part for input and output capacitors which supports upto 2.2MHz switching frequency with low ESR value.

Hello Steve,

I need to design the 0.8V@1.5A with this regulator. The ripple and Voltage tolerance requirement are 3mVp-p and tolerance is 3%.

Can I use this regulator to generate the 0.8V by 12 Vin?

Kapil, 

For the input cap, the actual capacitance will impact the input ripple to the converter.  Although the 5uF is the recommended minimum, that is really dependent on the supply and the required input ripple. 

The output cap DC bias derating is the most important to look at for both the input and output caps, as that will definitly impact the effective capacitance of the input and output.  The parts in the datasheet should be ok for the 2.2MHz applications as well as the 1MHz applications.

Hello Steve, 

Thanks for the clarification. What about my another query generating 0.8V. is the output ?

Thanks Steav.

Thanks Steve.

Hi

We will close this ticket.

BSR-MV

Shuai

Hello Shuai,

Wait, please don't close this ticket.

Hi Kapil!

Sure. 

Shuai

Hello Steve,

As we were facing issue in webbench to generate the 0.8V for PLL by changing the input voltage. Sharing the required input for validation and conclusion for your reference. 

 The requirement for BCM88280/BCM88480 0.8V PLL rail is

• Vin range: 3V-13V
• Iout Range: 0.1A-2.5A
• Ripple: 3mVp-p
• Voltage Tolerance: 3%
• Load Transient- 10% to 50%

Please Validate and Conclude of TPS62913 for 0.8V BCM  PLL.

Hi 

Steve will reply you tomorrow!

Shuai

Thanks for the details on the application condition.  Will the design really have a VIN that changes from 3V to 13V?  This is a very large input range and unusual for a single design.  If you have multiple designs that need 0.8Vout but have different input voltages, the solution will be different.  

I have been looking into the device performance and model for the low VIN and low VOUT conditions, and wil get back to you shortly with an update.

Can you confirm the normal input voltage for this design? 

Hello Steve, 

Please take 12V and 5V with 5% tolerance.

Hi Kapil!

Steve will reply you tomorrow!

Shuai