Other Parts Discussed in Thread: BQ79616
I mistakenly believed that in the below circuit, removing power from the NPN collector would cause LDOIN to go low thereby forcing the digital AND analog portions of the BQ79616 into a POR state. Hindsight: Bat pin is still powered and the NPNB and LDOIN still have power. After turn on (wake ping) when the supply (a BUCK converter) is then subsequently turned off the collector =~0V, the base shows 6.2V and the emitter (LDOIN) 5.5V. When we remove the collector power we believe that the digital portion of the BQ79616 goes into a different state (shutdown?). But it also appears that the analog portion stays powered albeit different than before. The original goal was to put the chip into the lowest current draw state possible with an added capability of "resetting" the chip outside of the UART if needed by cycling the collector. If we issue the shutdown command prior to turning off the BUCK we get the low power draw expected, just like when first applying BAT without the BUCK on initial power up. Also when we turn the collector voltage off our RX signal into the BQ79616 goes low.
Q1: With the RX staying low is the chip held in POR and therefore not comms timeout and then shutdown?
Q2: Will this state of the collector off, the NPNB/LDOIN being powered, and the RX low damage the chip?
Thanks.
