Will you please confirm if the following circuit is violating any of the ratings in the datasheet.
If yes, please help to provide any calculations on priority.
Also in case input / KL30F line may have +/- 150 volts for 50 msec or 5 seconds, which specifications will get violated if any.
We understand injection current for Vin > VDD is +/- 10 mA.
Thanks a lot Jesse for replay. Now agreeing ,VLSENSE = 35.6V, as you have calculated above, can we add series resistor R1 / R2 (for other line) to limit the injection current < +/- 10mA (Vin > VDD) as shown below? so in this case even if VLSENSE = 35.6V, will it damage the IC if we choose R1 and R2 to limit the current to 50% than given in the datasheet, for example 8.2k.
normal voltage on that line will be 8 to 18 volts.
one more idea, or the position of R3 and R4 is better since it will form RC filter as well, apart from limiting the clamp/injection current ! :)
Thank you Jesse. please help to understand on the specifications given in the datasheet for injection current in details. this is contradictory to above statement that even damping the current below specification's will damage from the over voltage. what is validation method for this clamp current from TI side. In case we want to validate this what are recommended tests / set-ups ? condition clearly says Vi > VDD is acceptable.
Since now we are talking about ESD, this levels are 4KV for HBM and close to 750Volts for CDM. Does this mean we can add 4 Mohm and 750K series resistor to pin to limit the current below 10mA respectively, in order not to damage the device ? assuming we dont want to use the ESD capacitors.
Its better to have a call. when can we set up call with Dev/Validation team ?
