LM5176: instability of PWM

Part Number: LM5176

Hi team,

my customer discover some  problem under 24 to 20V step down conversion

the load is 5A.

channel 1 is vout, channel 3 is SW,

you can see the PWM doesn't follow FCCM behavior,

May I know is this slope compensation problem or something else?

  

below is the schematic, they basically follow this file EPR_EVME3(001)_Sch_Dell.PDF

I try webench to emulate it but the phase margin looks fine, so weird... 

  • Hi Fred,

    thank you for using the E2E forum.

    Let me look into this, but due to a ongoing team training this might take a few days.

    I should be able to comment on this in the next 1-2 days.

    Best regards,

     Stefan

  • Hi Stefan,

    thanks for reply,

    I see, this is quite urgent. please provide me a compensation component that can fit all PD vout spec when you're available.

     but could you at least answer me first which BU make this file?5140.EPR_EVME3(001)_Sch_Dell.PDF

    is this from your team or system team

  • Hi Fred,

    no, this board has not been designed by our team. I will try to find out where this has been designed.

    I will look into this as soon as possible but as mentioned may take some time.

    Best regards,

     Stefan

  • Hi Fred,

    i have some struggles to read all the values in the schematic as the resolution is not very high.

    Can you try to fill in the data into the design calculator tool: LM5176 data sheet, product information and support | TI.com

    and pass it over to me.

    This would also clarify the input and output requirements. (input voltage range / output voltage and load)

    Thanks,

     Stefan

  • Hi Stefan,

    Copy of LM5176 Buck-Boost Quickstart Tool r1.0.xlsm 

    there you go, I don't know the ESR of capacitor and MOS information, but I don't think that dominate stability.

    and like I said they mostly  follow 2402.EPR_EVME3(001)_Sch_Dell.PDF  you can refer to  it.

    And as you might know PD3.0 have multiple output option ranging from 5V to 28V.

    could you also help  generate a compensation component that fit 5,9,15,20 and 28V output with same 24 input voltage?

    BTW the FB pin is connect to a DAC output to change vout, you might want to look into it.

    Regards,

    Fred

     

  • Fred,

    This looks like it might be a derivative of a design I worked on a while back, but with Stefan's support.

    I had similar ripple when the input voltage was close to the output voltage (19.6V input in my case) and I had incorrect compensation components. After changing to the attached values I saw a huge improvement in the output ripple.

    Your DAC control looks reasonable and shouldn't cause a problem. PC2387 will form a bit of a filter on the feedback loop but I don't think that would cause the ripple.

    Compensation tuning is my first recommendation.

    Here is what I am using (computed with Stefan's spreadsheet if I recall).

    Kind regards,

    Steve

  • Hi Steve,

    1.  for USB PD 3.1 application, which is the bottleneck of stability ?   5V/3A or 28V/5A?

        BTW, my customer Vin is 24V

    2. In the meantime, I just got the new schematic from PD controller team, have you involved this?

    see attached EPR_SRCE1(001)_Sch.PDF

    3. there's a strange thing happen, like I said they discover abnormal PWM behavior in every PD possible output with Rc1=2.4k and Cc1=27nF.

    but when they change to Rc1=10k, Cc1=270pF, it somehow work stable again,

    but the bode plot looks failed to me in the calculator. and decreasing the RC of compensation is supposed to be worse since it push the zero farther,

     how did it happen?

    update schematic ROSA U3224KZ_C3_SD IF BD_PD DCDC (002).pdf

  • Hi Fred, there is always some difference between the mathematical model (e.g. done with the Excel, or other tool) and the real hardware as all the board and components parasitics can not be considered. To get the right value a measurement on the board with a vector network analyzer would be required.
    Not sure what Steve will recommend here but i would be really go to measure the real loop compensation performance on the board.
    There is also a very low Slope compensation capacitor used. You might try to increase this to e.g. 470pF to avoid a too high slope compensation.

    Best regards,

     Stefan

  • Hi Stefan,

    one question here,

    theoretically there are three pole around KHz (load pole and LC double pole)  but only one compensation zero.

    but it doesn't match the plot here, I only see extra one pole effect here ( from -20dB/dec to -40dB/dec) 

    where is the missing zero that cancel that one LC pole?

  • Fred,

    Unfortunately I can't comment much more than stating the compensation observations I saw on my board. I am not an expert on DCDCs so can't help with the Bode plots. I simply used the suggested values from the calculator.

    Your compensation circuit has a different structure to what I used and seems to only have the snubber part, missing the parallel capacitor so I really can't comment on either its behavior or component values.

    Did you try using the values I am using in your Bode plots and/or on your board?

    Regarding the updated schematic you sent, I am not directly involved in that. It also looks like it is a different DCDC controller.

    Sorry I am not more help.

    Kind regards,

    Steve

  • Hi Fred,

    sorry, got wrong - we have a current controlled system. So the power stage is as shown here: https://www.ti.com/seclit/ml/slup341/slup341.pdf

    page 3-12

    Best regards,

     Stefan

  • Hi Stefan, Steve,

    they connect VOSNS  directly to DAC output, I don't see the meaning why ?

    is this making extra pole or zero at FB pin that potentially causing instability?

  • Hi Fred,

    R2342 should not be assembled on the Board. Having this resistor in does not work. 

    Best regards,

     Stefan

  • Hi Stefan,

    Thanks for your reply even though busy

    how about PC2387, does that create low frequency pole that unnecessary ?

    Regards,

    Fred

  • Stefan,

    The purpose of R2342 is to ensure that if the DCDC is enabled before the DAC is configured that the output voltage is limited to about 12V.

    Without this resistor if the DCDC is enabled and the DAC is not configured then the output voltage will go to its maximum value (50V in my case).

    This is because the DAC is a voltage DAC that powers up with a floating output. Once the DAC is enabled it will effectively over-drive R2342 hence effectively remove it from the current steering.

  • Fred,

    The purpose of capacitor PC2387 is to limit the slew rate on a voltage change. Without this capacitor a step change in the DAC output will cause a VERY fast step change in the output voltage (violating the spec).

    This does not create any poles etc... since it is not in the dynamic control loop. It is really only filtering the DAC output.

    Regards,

    Steve

  • Hi Steven,

    I appreciate your explanation ,

    but would you elaborate on the dynamic control loop part?

    since the path from Vout to VFB did pass several R and C, not to mentioned the vout is directly connect to DAC,

    so I guess this definitely introduce unexpected pole, please correct  me if I'm wrong , thanks

    Hi Stefan, 

    I also expect your feedback on this part, thanks.

    Regards,

    Fred 

  • Fred,

    I am not a control loop expert so you will need to do a Bode analysis if you want/need it.

    VOut is not really directly connected to the DAC, but as you say the loop does have capacitors and resistors. The "direct connection" through R2342 becomes irrelevant once the DAC is enabled since both sides are very low impedance compared to the resistor value, hence dominate. The capacitor is really no different to typical DCDC configurations where a capacitor can be placed on the FB pin to reduce the effects of load transitions and/or increase response (when on the high side). I agree that the stability needs to be checked, but it is a fairly common practice.

    If you want to remove the filter capacitor then you can, but you will then need to make sure that there is not a step change in the DAC output.

    Basically, all I can really comment is that this implementation works for me in my scenario. My specific design was not intended to be guaranteed to be stable across all conditions nor used as a verified customer solution. It was for an internal development of other features of our project to provide a variable 3V to 50V supply.

  • Hi Steven,

    thanks and

    no offense,  just trying to find the root cause for the customers, I'll do the bode plot analysis on the board if needed,

    but like you said normally we add capacitor at high side of FB resistor to help transient, but not sure if the low side in this case has any side effect or not.

    I'll also wait and expect Stefan  comment on this who will be back tomorrow

    thanks.

  • Absolutely :)

    I will help wherever I possibly can but this is a little outside my realm :)

    I don't think that cap is affecting anything.

    I DO think that the compensation needs to be tuned though.

    Did the customer try the configuration I am using? I checked 24V in 12V out at 3A and it looked reasonable.

    Let me know if I might be able to help , but as I say, I am not a DCDC expert or analog designer.

    Regards,

    Steve

  • Hi Fred,

    i would like to follow up on and point which was discussed somewhere above but I have not seen an updated on that:

    "There is also a very low Slope compensation capacitor used. You might try to increase this to e.g. 470pF to avoid a too high slope compensation."

    Thanks,

     Stefan

  • Hi Fred,

    I have not seen an update on this thread for the last 14 days.

    Have all questions now been clarified and answered. 

    If yes, please click on the resolved button, otherwise let me know with the required details.

    Best regards,

     Stefan