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[FAQ] LP87561-Q1: How can I use LP875x-Q1 PGOOD as nRESET signal for SoC

Part Number: LP87561-Q1

This FAQ applies to LP8752x-Q1 and LP8756x-Q1 devices. 

In LP875x PGOOD monitoring is masked with EN signal, meaning when bucks are disabled the PGOOD is not monitored and the signal is high. This is done to allow combining several PMICs and disabling rails (for example suspend to RAM mode etc.) without affecting PGOOD monitoring. But when PGOOD is used as a nRESET signal this can be problematic. For example on shutdown the PGOOD stays high, when the SoC reset signal should go low. 

Workaround for this is to combine the PGOOD signal with one of the GPIOs. GPIOs can be EN pin controlled with programmable delays as the same as for the buck outputs and GPIOx can be used to keep the PGOOD low at startup for predetermined time and also pull PGOOD low at shutdown immediately. When combining PGOOD with GPIOx both should be set as Open-drain outputs and then the signals can be tied together. Pull-up resistor to IO voltage would be needed. 

Alternatively the PGOOD can be combined with a reset signal from the uC, or with some discrete power device PGOOD which behaves as nRESET signal (when rails are disabled nRESET goes low).