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[FAQ] LP8732-Q1: How can I used LP873x PMIC PGOOD as a nRESET signal for a SoC

Part Number: LP8732-Q1

This FAQ applies to LP8732x-Q1, LP8733x-Q1, LP8732x, LP8733x devices. 

In LP873x PGOOD monitoring is masked with EN signal, meaning when bucks are disabled the PGOOD is not monitored and the signal is high. This is done to allow combining several PMICs and disabling rails (for example suspend to RAM mode etc.) without affecting PGOOD monitoring. But when PGOOD is used as a nRESET signal this can be problematic. For example on shutdown the PGOOD stays high, when the SoC reset signal should go low. 

Workaround for this is to combine the PGOOD signal with one of the GPIOs. GPIOs can be EN pin controlled with programmable delays as the same as for the buck outputs and GPIOx can be used to keep the PGOOD low at startup for predetermined time and also pull PGOOD low at shutdown immediately. When combining PGOOD with GPIOx both should be set as Open-drain outputs and then the signals can be tied together. Pull-up resistor to IO voltage would be needed. 

Alternatively the PGOOD can be combined with a reset signal from the uC, or with some discrete power device PGOOD which behaves as nRESET signal (when rails are disabled nRESET goes low). 

Note that in LP873x devices there are two PGOOD modes, gated and continuous mode.

In gated mode the PGOOD is gated for 800us in startup (from time buck/LDO is enabled) to allow outputs to rise to target voltage. If the voltages are settled within this gating window the PGOOD stays high during the whole startup sequence. Only if some of the rails takes longer than 800us the PGOOD is triggered and goes low. Note in gated mode the the PGOOD works always 'latched' meaning it needs to be cleared either by power cycling or with I2C write.

In continuous mode the PGOOD goes low during startup until output voltage reaches the target voltage window. In continuous mode the PGOOD operation can be wither real time status or latched, which can be selected with register bits.