Hi Team,
Could you help our customer's concern.
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi Team,
Could you help our customer's concern.
Hey Jonathan,
The gate bias voltage necessary to turn on the FET connected to Cell 1 is generated by the resistor RINE connected to VC0. Make sure RINE is 1kOhm, and CINE is 0.1uF. The gate should have a threshold voltage less than 1.7V. This is outlined below Figure 9-2 in section 9.3.4 of the datasheet. VC0 does contribute to the balancing transistor being turned on and off. When stacking devices, VC5 will not be used to turn on the transistor for VC6. VC0 of the upper device will do that. Make sure to keep the VC5 of the lower devices and VC0 of the upper devices separate.
Thanks,
Caleb