CSD19538Q3A: PSE Mosfet Protection

Hello David,

Thanks for the inquiry. Protection for the FET is dependent on the application and requirements. Please keep in mind, that you must avoid overvoltage stress from drain-to-source (BVDSS or avalanche breakdown) and gate-to-source (abs max VGS). TI rates our FETs for single pulse avalanche although this condition should be avoided. We do not rate our devices for repetitive avalanche. I am going to pass this onto our PoE apps team to get their input as well.

Best Regards,

John Wallace

TI FET Applications

Dear Penny,

we revived the document multiple times, there are no written guidelines in the document or am i missing something?

There is only a Schottky diode in the schematic TIDA-01411 (10MQ100NTRPBF), and i saw this before asking the question, what is the logic to choose the protection for PSE mosfet?

Best Regards,

David.