UCC21520: I am having problems with my OutA_1 and OutB_2

Ikenna Chukwuka

Part Number: UCC21520

I did my simulation on LTSPICE but I do not understand why I am getting signal for both outputs looking this way.

om the simulation result, Vdda_1, which is 20V, has a very bad ripple. The outa_1 signal does not look good, the same as outb_2.

Can you please help me out here? I'm not sure why I'm getting so much ripple, and the outb_2 voltage is too low at 2.34V compared to the outa_1 voltage of 17.2V.

Regards,

over 1 year ago

0 Olivia Brandel over 1 year ago

TI__Intellectual 835 points

Hi Ikenna,

I would recommend reviewing this application note on selecting bootstrap circuitry for half-bridge configurations.

I noticed at least one area in your schematic that differs from our recommendation: the ratio of C_VDD to C_BOOT. I’ve reproduced the relevant application note section below (sect. 3.2).

The charge to replenish the bootstrap capacitor must come from some larger bypass capacitor, usually the VDD bypass capacitor. As a rule of thumb, this bypass capacitor should be sized to be at least 10 times larger than the bootstrap capacitor so that it is not completely drained during the charging time of the bootstrap capacitor. This allows the bootstrap capacitor to be properly replenished during the charging sequence. This 10x ratio results in 10% maximum ripple on the VDD capacitor in worst case conditions. C_VDD ≥ 10 × C_BOOT.

Additionally, section 10.2 in the datasheet provides recommended values for other key components like the input filters, VCC capacitor, etc.

Please take a look at the documentation and see if these recommendations improve your simulation. If you still are not getting the expected output, please let us know and we can review the schematic in more detail.

Thank you!

Best,

Olivia Brandel

0 Ikenna Chukwuka over 1 year ago in reply to Olivia Brandel

Prodigy 170 points

Hello Olivia,

I found this information very helpful, but I am still having some issues with the Gate Drive. v(hv_g) and v(hv_g_1) are pulling to 20V but not producing the expected output, and v(lv_g_2) is also not looking good, except for v(lv_g), which appears to be fine. I need your help here.

Circuit now with two Gate Drive Running:

Fig.1

Result:

Fig.2

0 Olivia Brandel over 1 year ago in reply to Ikenna Chukwuka

TI__Intellectual 835 points

Hi Ikenna,

Sorry to hear that you are still seeing issues. Can you share a simulation image with all 5 signals (like you shared originally) so I can understand the problem better? Also, can you share the input side of the circuit again if you changed any component values?

I will take a look at the info you share and see what other observations I can find.

Best,

Olivia

0 Ikenna Chukwuka over 1 year ago in reply to Olivia Brandel

Prodigy 170 points

I can send it to you as a zip file. If you share your email, I can get it out to you now. I have looked at the datasheet and still do not understand why only one is switching.