• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 62 subscribers
  • Views 163 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TPS3703-Q1: Glitch immunity to sensor pin at UV/OV

TPS3703-Q1: Startup delay

Andreas Nestler
Intellectual 310 points
Part Number: TPS3703-Q1

Hi,

we are using TPS3703A4120 device, which provides a fixed reset delay time of  10 (+/-3) ms. At startup the startup delay has to be added which typ. 300us.

Q1: What extreme values can we expect for startup delay? Especially the max. value is of interest.

Q2: According note 4: "During the power-on sequence, VDD must be at or above VDD (MIN) for at least tSD + tD before the output is in the correct state". So, reset output assertion starts if VDD has to reach at least 1.7V and SENSE input has within range voltage. Is this correct? What means "...for at least tSD+tD"? Could this be even longer time and if yes what is the max. time tSD+tD?

Q3: Section 9.1.2 CT Reset delay time: "To determine which option is connected to the CT pin, an internal state machine controls the internal pulldown device and measures the pin voltage. This sequence of events takes 450 μs to determine which timing option is used." This parameter is not listed at all in datasheet timing requirements (section 7.6). How does this value apply. Is this an additional delay?

Please note: all those questions pop up after comparing measurement results (tD_measured = 13.21 ms) with the maximum expected value according datasheet (13 + 0.3 ms). Even with consideration of the startup delay we are at 25°C close to the maximum value according worst case analysis, which is weird.

Thanks in advance!

Best Regards,

Andreas N.

  • 0
    TI__Genius 11300 points

    Hi Andreas,

    Thank you for your question.

    Q1:  The startup time should be consistently 300us. 

    Q2: Yes, the VDD has to be equal or greater than 1.7V for tSD + (tD)*+/-30% for nRESET output the correct response to the value of SENSE pin. 

    Q3: This spec does not effect the timing delay of the Reset, This time initiates once SENSE pin enters the valid window and nRESET deasserts.

    Yes, in 25C you should not see the maximum values. Are you able to provide the schematic for your design?

     

    Jesse 

  • 0 in reply to Jesse Villanueva
    Intellectual 310 points

    Hi Jesse,

    Q2: tSD + (tD)*+/-30% -> Dou you mean tSD + tD*(1+/-30%) ?

    Q3: I have not really understood the answer. So, did I get it right that at power-up the time does not play any role? So the 450us will not add e.g. to the fixed delay of 10ms (+/-30%)  if CT is OPEN?

    Below you find the schematics:

    and the scope screenshoot with ch1 = 1.2V and ch2 = Reset output

    Best Regards,

    Andreas N.

  • 0 in reply to Andreas Nestler
    TI__Genius 11300 points

    Hi Andreas,

    Yes, I meant tSD + tD*(1+/-30%) .

    Yes the 450us does not add additional delay at start up.

    Is it possible if you can put a pull up resistor on the CT pin, just to double check that timing?

    Jesse