TPS65023: Output voltage issue

Hi Zhang,

I've assigned this thread to our device expert. He should get you an update by tomorrow.

Thanks,

Gerard

Hi Zhang,

Could you provide a scope capture of the switching node before the inductor on all three bucks during power up? I would like to see what the waveform on L1, L2, and L3 looks like.

Regards,

James

Hi James,

Please refer to below formwave for the DC/DC1=0.9V, DC/DC2=1.2V, DC/DC3=0.8

DC/DC1: Output voltage is 0.9V

:

DC/DC2: Output voltage is 1.2V;

DC/DC3: Output is 0.85V;

Hi Zhang,

Thank you for providing those captures. I have an EVM that will be populated with the same resistor components on the DEFDCDCx inputs that you showed in your schematic. Once I get that board back with the components in place I will run some power up tests and update you here. I should have more information within 2 business days.

Regards,

James

Hi James,

Many thanks for your kindly support, will wait for your testing result and we will communicate how to solve this issue, thanks.

Hi Zhang,

My pleasure, I'll get back to you soon.

Regards,

James

Hi Zhang,

The soldering request is still processing but I expect it to be done by Monday, I will get you another update by the end of the day Tuesday (2 business days).

Regards,

James

Hi Zhang,

The soldering request is taking longer than I anticipated. There is likely a backlog of requests right now. I will continue to check for the EVM but I did some additional tests on an alternate board.

This board is operating with the default voltage settings since it does not have resistor divider networks set up. However, I captured the start up waveforms for DCDC1, DCDC2, and DCDC3. I am not seeing the same ripple effect at the start of the power ramps but I would like to try this test on a board with the resistor dividers. Also, this EVM is not connected to a load or processor. I will include the scope captures below.

Would you be able to send me your layout so I can take a look while the solder request finishes processing? Also, if it's possible can you disconnect the PMIC or the power rails from the processor and test the power up waveform again? Does the transient response change if there is no load on the device?

The EVM I'm testing has a User's Guide that shows the capacitance on each power rail. It looks like they are using less capacitance than in your design. It may be helpful match the EVM specs and see if that improves transient performance.

Slow VIN ramp: CH1 - VIN, CH2 - VDCDC1, CH3 - VDCDC2, CH4 - VDCDC3

Fast VIN ramp: CH1 - VIN, CH2 - VDCDC1, CH3 - VDCDC2, CH4 - VDCDC3

Regards,

James

Hi James,

Thanks for your detail testing procedure for the TPS65023, and we test our board again and the result as below:

1. We start the DC/DC3 according to the default voltage 1.8VDC, the start waveform as below( the ripple effect at the start is small):

2. We start the DC/DC3 according to the external resistance feedback(for example 1.8VDC), the waveform as below(the ripple effect at the start is obvious):

3.The light and heavy load are the same effect for the waveform, and we can't disconnet the load;

4. I modfiy the design of the load capacitor to 22uF, but the testing result is same;

5. Layout for your kindly evaluating:

1) Layout top silk layer:

2) Layout top layer

3) Layout power layer:

4) Layout signal layer

5)Layout bottom layer:

Hi Zhang,

Thanks for providing all the information. I will take a look and get back to you early next week. I will also consult one of the other engineers who has handled this part to see if they have any additional insight.

Regards,

James