I'm doing performance estimation of an LLC isolated dc-dc converter with referring to the document "UCC25800-Q1 Ultra-low EMI Transformer Driver for Isolated Bias Supplies" (file name SLUSDX3B.pdf).
In that, there is a "SW-pin parasitic capacitance" in page-30 with the symbol C_SW and a typical value of 170pF.
Not crystal clear for me is the definition of this parasitic capacitance. One of the terminals of the C_SW must be the SW-pin (pin-7 of this IC) but what is the other terminal, i.e. C_SW is the parasitic capacitance between the switch-pin and where? Can we imagine the parasitic capacitance being added as an equivalent circuit component to the block diagram in page-10?
Also, how was it measured, e.g. with what frequency and excitation voltage or current amplitude? The the typical value is 170pF. Then, what is the reasonable assumption for piece-to-piece variation, frequency sensitivity and temperature sensitivity?
I don't find such information after several attempts on the web, so wondering if anybody can help to find it out.
Thank you!
Jun
