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# UCC28180: Frequency Dithering example

Part Number: UCC28180
Other Parts Discussed in Thread: TLV3201

Hi,

I'm trying to simulate a PFC Dithering circuit based on the SLUA704 document using a UCC28180 and TLV3201. R4 and C1 are designed to get a dither rate of 2kHz. However, using the given resistance and capacitance values of 33kohm and 16.4nF, when simulated I obtain a dither rate of ~1.3kHz instead of the 2kHz I expect. Also, a period of 500us is used for the calculation (from the rate of 2kHz). Should it not be 250us since charging and discharging times are half of the period? Is there anything else that I'm missing?

Thanks

• Hi Santhosh,

Ray

• Hi Santhosh,

Thank you for the query.

You are correct in your observation.

1. Simulating the same circuit gives 1.3khz dithering frequency rate and so I would advice the following modifications to be made:

C2 is a 1nF capacitor to AC couple the signal from the comparator output to RT/FREQ pin. The orignal bias current applied at the RT pin is 45.8uA i.e (3-1.5)/32.7k . The variation in dither curent is in the range of +/-4.9uA. We can choose a reasonable series resistor of 17.8k(R4) and knowing that the voltage difference across the resistor will on average be (3V-1.5V) = 2.5V, we will have both a charging and discharging current of 84uA to a capacitor.

2. The capacitor is selected according to the dither rate. Let's say we need to discharge C1 from 2V to 1V. The dither rate is 500us, but the time for capacitor to dicharge will be 250us. Using I = Cdv/dt, we get C1 as 21nF.

3. Finally R6 can be chosen approximately to be (2-1.5)V/4.94uA = 101kohms.

4. From the graph above, we can see the dither rate is around 540us.

Please let us know if you have clarifications. Hope this helps.

Thank you

Regards,

Harish

• Yes this technique works, and makes more intuitive sense too. Thanks!