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Original question:

LM5025A: Fast switching gate signal during overlap

LM5025A: Secondairy side FETs break down

Teun Teeuwen
Prodigy 70 points
Part Number: LM5025A

Hi,

I have a design with the LM5025A in whitch the FETS on the secondairy side of the transformer break down all the time even tough they are very over specified. I used the exel sheet on the  LM5021A product page to calculate most of the components. Following that 80V FETS should be enough, but I even used 150V/31A FETS and they still break down. I used DFN-56 on the design.

I have also used IRF200B211 (TO-220) and those are so far the only FETS that haven't broken down. 

I haven't measured spikes over 60V on the signals so I don't understand why the FETS keep shorting out.

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1082706/lm5025a-fast-switching-gate-signal-during-overlap/4018134

Here is a previous post of mine for the schematics etc.

  • 0
    TI__Mastermind 26415 points

    Teun,

    The E2E thread you referenced is from 3 months ago and seems to be asking the same question you are posting here in this thread. Are you still having the same SR issue? The focus of the discussion previously was on the transformer dot polarity, the clamp and the CS resistor - have all power stage issues now been been resolved and you are still having SR issues? What about the high temperature of LM5025A - has that been corrected? If all/any corrections have been made then the schematic posted in your original thread is probably not up to date? Let me make some general comments about active clamp and the use of self-driven SR.

    It seems the focus of your observation of SR failure has previously been related to SR voltage rating. There are other potential SR failure mechanisms related to this topology that I want to make you aware of:

    1. SR timing from primary to secondary. If the secondary SR timing is not synchronized to the primary there can be situations where the secondary is conducting while the primary is not or the secondary is not conducting while the primary is. One way to check the timing is to remove the secondary SR MOSFETs and temporarily replace them with diodes. Now there is no timing issue but you can still measure the respective SR gate drives compared to the primary side timing.
    2. SR timing between SR1 (Q4) and SR2 (Q2) is important because we want enough dead time to avoid cross conduction but not so much dead time that we incur unwanted body-diode condition loss.
    3. Self driven gate drive amplitude. Your schematic shows a self driven SR gate scheme where the gate drive amplitude is not regulated. The amplitude of the SR gate drive is proportional to VIN according to the transformer turns ratio. What is the amplitude of your SR gate drives over the full range of VIN? You need to verify that there is enough amplitude to fully enhance the SRs under all design corner cases. Refer to section 4.1.4 in Designing for High Efficiency with the Active Clamp UCC2891 PWM Controller.

    Regards,

    Steve M

  • 0 in reply to Steven Mappus1
    Prodigy 70 points

    I have resolved some of the issues on the prototype board so the schematics are indeed not 100% correct.

    I think you are right about the gate drive ampiltude. But I'm still looking into that.

  • 0 in reply to Teun Teeuwen
    TI__Mastermind 26415 points

    Yes,

    Check the behavior of your MOSFETs over the worst case gate drive amplitude and temperature. When the SR gate drive is low, the RDS_on is increasing which makes the temperature increase, further increasing the RDS_on and this can lead to thermal runaway failure. Since you mentioned you have SR MOSFETs that are working in your circuit, try adjusting VIN to the point where both SRs are receiving an optimal amount of gate drive amplitude. Measure the temperatures at this point and then vary the input voltage while continuing to monitor the SR gate drive amplitude and measure the temperature change as you move above/below wherever that optimal point was previously measured.

    Regards,

    Steve M

  • 0 in reply to Steven Mappus1
    Prodigy 70 points

    Is there a 12V output reference schematic available for the LM5025A?

  • 0 in reply to Teun Teeuwen
    TI__Mastermind 26415 points

    Teun,

    I only see two available ref designs here on TI.com and both are 5V output. Attached is a 15V output ref design not available on TI.com but we made this one for a specific customer. This is the closest I can find to a 12V output. I hope this helps.

    PMP4473 Schematic.pdf

    PMP4473 BOM.xlsx

    Regards,

    Steve