TPS23753A: How to fulfill the power up sequence and power down sequence of LM3881.

Hello Kanta,

To clarify, in your design, you want the EN pin to trigger from the output voltage from the TPS23257A, not an external trigger?

Thanks,

Broughton

Hello Broughton,

That is correct.

I want to operate the EN pin of the LM3881 by triggering the output voltage from the TPS23257A.

Hello Kanta,

After looking into this for a while I've come up with two options.

The first is taken from the LM3880 data sheet here (see Figure 8-5 on page 16): https://www.ti.com/lit/ds/symlink/lm3880.pdf. This shows a solution for configuring the Power-up sequencing from the same input voltage signal. However, if you want to configure both Power-up and Power-down sequencing it requires an independent external signal. Therefore, according to this data sheet, you can only meet Power-up sequencing requirements.

The second option is a design I developed:

Rise Sequence: The resistor network R1/R2 is just a voltage divider that should be set to the EN threshold voltage. The C1 capacitor is probably not necessary for this but I included it anyway. This resistor network will keep EN low until VCC is high enough to turn on the IC. 

Fall Sequence: When 5V goes low, the EN pin will drop to low immediately as well. The bulk capacitor (CB) will then need to be large enough to supply the LM3881 along with whatever else is on the load for the 25 clock cycles necessary for the fall sequence. The diode will isolate the EN pin from the bulk capacitor. The bleeder resistor (RB) will need to be a relatively high resistance value. 

A concern I have is that the bulk capacitor (or possibly multiple capacitors in series) may end up being quite large once you do the required calculations for the capacitance value. This design is by no means guaranteed to work.

Let me know if you have any further questions!

Thanks,

Broughton

Hello Broughton,

Thank you for your response.

How many capacitor capacitances(CB) are required to meet the power down sequence?
I would appreciate it if you could also tell me how to calculate this.

Also, the power down sequence requires 40 clock cycles to be supplied; why is 40 clock cycles necessary?
Is the time for the EN pin to fall in addition to the time for the FLAG1 pin (Td4), FLAG2 pin (Td5), and FLAG3 pin (Td6) to all fall?

Hello Kanta,

I was incorrect about the 40 clock cycles. After looking at the data sheet, it is actually 25 clock cycles (9 + 8 + 8). Worst case scenario is 26 depending on where EN is asserted relative to the clock signal. Sorry about the confusion there.

I am attempting to run a simulation of my proposed solution above but am encountering some issues during start-up while the capacitor is charging. I will update you on this as quickly as I can but I don't know if its possible to meet both power-up and power-down sequencing without an external signal. 

Thanks,

Broughton