This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

REF6050: Capacitance on reference voltage with one REF6050 driving many ADS8866s

Part Number: REF6050
Other Parts Discussed in Thread: ADS8866, REF5050, TIPD211, ADS8900B, OPA836

I'm hoping to use two daisy-chains of ADS8866 ICs in a multichannel simultaneous sampling system running at 50kHz. I currently have over twenty ADCs in the longer of the two chains, and I'm worried about the aggregate capacitve load on the REF pins, which are driven by a single REF6050 (i.e. one REF6050 per chain).

Both ADS8866 and REF6050 data sheets recommend a 22uF to 47uF capacitor on the ADC REF pin, and the REF6050 data sheet sepcifies a maximum of 47uF for stability. Obviously with >20 ADCs with 47uF each I have over an order of magnitude more capacitance than this.

My questions are:

Has anyone ever tried using a single reference IC with this many ADCs? (I note the TIPD211 reference design has a single REF5050 driving four ADS8910s with 10uF each, but I wouldn't want to extraploate very far from that).

If not, is there something I've missed that means it will work fine and I'm worrying about nothing?

If not, is there a cheap and easy way to fix it?

There is currently nothing but ~100mm of PCB track between the reference output and the ADCs' REF input. I considered adding a series resistor at each ADC, with the ADC REF pin connected on the capacitor side, but even one ohm creates a low-pass corner well below the sampling rate.

My calculations suggest that 47uF is quite generous. Assuming the typical REF current of 35uA is drawn for 10us from a 47uF capacitor:

Q=CV, Q=It -> CV=It -> V=It/C -> V=(35u*10u)/47u=7.447uV

For a 5V reference that's a relative error of 1.489u, or 2**-19.3. To my eye this is better than needed for a 16b ADC, and the REF6050 data sheet states it is good enough for 18b. I could probably live with 13b, so I could reduce every capacitor value to keep the total under 47uF, perhaps putting larger capacitors on the ADCs handling critical signals and smaller ones on those just monitoring quasi-DC levels.

All suggestions welcome.

  • Hi Ross

    There are multiple options for your problem - 

    • You can use a SAR ADC with internal buffer and use one reference eg. ADS8900B + REF50 as mentioned in TIPD211 
    • REF 60 can easily drive 2 of them as you are using it at low sampling frequency. 
    • You can use REF50 with external buffer. 

    Can you please tell what is your signal levels , ENOB and how much error budget [tempco , noise , aeging] you have allocated for refences. We will help you to narrow down the optimum series reference. 



  • The ADS8900B is eight times the price of the ADS8866, and I need thirty. Economically it would make more sense to stick with the ADS8866+REF6050 and fit one reference per ADC. Also, the ADS8900B is availble in only QFN packages. My soldering tools and technique aren't good enough to reliably attach all thirty to the PCB. But it's a nice looking part, and I'll bear that family in mind for future applications.

    The REF60xx may well be able to drive two ADS8866s at lower sampling rates. I need to drive at least twenty, and I can't drop the sample rate below 25kHz.

    I considered using an external buffer, but won't that just push the problem onto the buffer IC? If the REF60xx's internal buffer isn't stable with >800uF capacitive load I would expect an external buffer to have a similar problem.

    Some application background:

    This design is intended for use to analyse and characterise a "black box" my client has ended up with. I will build only one unit, and it will be used for only a few weeks in a controlled lab environment. Advantages of this are that changes with ageing and temperature can be safely ignored. Disadvantages of this are that I need to keep the NRC low, which means quick, easy design choices, and hand soldering.

    Based on my experience with similar black boxes in the field, I have "designed" the ADC circuit by assuming that sixteen bits at 50kHz is good enough, copying ADC8866 data sheet figure 53, and adjusting the OPA836 feedback network to reduce the gain and add a filter. I am hoping to get close to 15ENOB without thinking too hard.

    Since my engineering time could be measured as ten REF6050s per hour, I think the answer is to fit one reference per ADC and not think about it any more. I was hoping someone here might have tried the one-reference-many-ADCs approach, or knew off the top of their head that it definitely would (or would not) work. If you have any such immediate knowledge that would be great. If not, don't spend any significant time on it. After all I'm not going to spend more than two more hours on it, and I'm getting paid.

  • Hi Ross 

    Thanks for detailed description of your application. As I can see that noise is the key care in your system. The best solution for you would be to use external buffer with REF50, external will have better drive capability than ref60 internal buffer. You can look into ti op amp portfolio -

    Let me know if you need further help. Good luck with your design.