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[FAQ] TPS6594-Q1: LP8764-Q1: Debugging PMIC Behavior with Interrupt Interpretation.

Part Number: TPS6594-Q1
Other Parts Discussed in Thread: LP8764-Q1

This FAQ is relevant to TPS6594-Q1 and LP8764-Q1 Devices.

If your PMIC is failing to communicate via I2C or SPI, the issue is likely to lie in supply or component selection. It will be best at this stage to confirm the supply voltage and component values are as specified in the PMIC datasheet. You can use an EVM to communicate with the IC by using this guide.

If communication with the device is functioning, the entry point for debugging PMIC Behavior is by reading the Interrupt registers and interpreting them to analyze the possible source of error. Registers of particular important are 0x5A INT_TOP, 0x69 INT_FSM_ERR, and 0x6C INT_ESM; these provide an entry point by which you can narrow down more relevant interrupts. Reference the Hierarchical Structure of Interrupt Registers figure in this datasheet section to narrow down the most pertinent interrupt. By reviewing the Interrupts sections in the datasheet, you can narrow down the potential cause for each interrupt. It can be useful to reference interrupt masking and other static register configurations to help narrow down the cause of a given interrupt.