BQ76952: Short-circuit protection time100ms

Hi Bright,

Are you measuring the short-circuit event to the DCHG and DDSG pins on a oscilloscope? Can you share the waveforms?  

Best regards,

Matt

Hi Matt

Thanks for your reply.

1.blue--Current WAVE

2.Yellow-DDSG WAVE

3  Sample Res:5mΩ

Thanks Bright. Can you also send the .gg.csv file (saved register settings) from BQStudio? Is it possible this is the OCD1 or OCD2 protections you are seeing?

Thanks,

Matt

KGBQ76952.gg.csv

FYI,Thanks

Hey Bright,

Matt is out of office till Friday. He'll get back to you as soon as possible.

Thanks,
Caleb

Hi Bright,

Looking at your register settings, it looks like you have the OCD2 threshold = 200A and the SCD threshold is 200A. So you might be observing the OCD2 timing.

I also notice the settings are a little strange. OCD1 is set to 18A and 16.5ms delay. Normally OCD1 is set higher than the OCD2 threshold. And SCD is set higher than OCD1 and OCD2 normally. Can you try setting different thresholds for SCD and OCD2?

Regards,

Matt

Hi Matt

SCD, OCD1 and OCD2 are set correctly, but the short-circuit protection waveform is wrong.

You can use this configuration to test?

Hi Bright,

Can you set different thresholds for SCD and OCD2 and test again. SCD should be set higher than OCD2. This will verify that you are observing the SCD fault for sure and not the OCD2 protection. I am not sure I understand why you would want to set these at the same exact threshold.

Regards,

Matt

Hi  Matt

Sorry later for reply .

SCD :10mV OCD1:6mV OCD2:4mV

Rref:0.2mΩ

blue:DDSG WAVE

Yellow:current wave

Hi  Matt

Sorry later for reply .

SCD :10mV OCD1:6mV OCD2:4mV

Rref:0.2mΩ

blue:DDSG WAVE

Yellow:current wave

Hi  Matt

Sorry later for reply .

SCD :10mV OCD1:6mV OCD2:4mV

Rref:0.2mΩ

blue:DDSG WAVE

Yellow:current wave

Hey Bright, 

I can't seem to make out the scale. What is your time per division?

Thanks,
Caleb

100ms per division

Hey Bright, 

Can you check your CHG FET Protections A and DSG FET Protections A registers? Incorrectly setting these registers can delay FET turnoff action by up to 250ms. See the descriptions above Table 13-21 and Table 13-24 of the Technical reference manual for the correct register configurations. 

CHG FET Protections A should only be set to 0x98 or 0x18.
DSG FET Protections A should only be set to 0x80 or 0xE4.

Thanks,
Caleb

CHG FET Protections A  0x18

DSG FET Protections A  0xE4

configurations are correct !

Hi Bright,

I don't see a problem with these settings. I will test this out on my board tomorrow to verify.

Regards,

Matt

Thanks  !