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LM5069: Part failed and will not start

Part Number: LM5069

Hi,

I have an application where I'm using an LM5069 to control and current limit a battery input which can be from 42-60V. This has been working fine and rolled out to a wider population of boards but I've now had a failure of a part on a customer unit.  This part was tested when built and has been running successfully for many hours (probably several hundred). Now it will not power up.

We've taken scope traces and can see that Ctimer voltage increases up to, and stays at, 6V as soon as VIN is applied with UVLO held low. This normally ramps to  ~4V and then is discharged. When UVLO is negated (using an opto), there is no change of state of the device. The Gate-Source voltage remains around -1V.

We have performed an A-B-A test, replacing the part on the board, and the fault follows the LM5069 component. We've also taken resistance measurements of each pin to GND when the part was removed which shows a lower resistance (500kOhm) on the TIMER pin compared to new parts.

Results, schematic and part marking can be seen in the presentation here.

The only risk factor I am aware of is that there is a high inrush condition on this variant of the design when a large external capacitance is connected to the supply once it is up and which occurs on each startup cycle. That causes the LM5069 to go into "circuit breaker" mode (current > 2x configured limit) and then restart by charging the additional load in power limit. Though the output voltage drops substantially during this time, this has been characterised and found to work successfully in our application.

I really need to understand the root cause and whether there is anything in the design that could have caused it and whether the remaining field population are at risk of the same failure occurring.

Thanks,

Paul.

  • Hi Paul,

    From your below statement, I understood that the load is getting hot-plugged in your application, which is different from the normal hot-plug use case. How the load is connected ? manual or through another relay switch ? Any suspect on the possible ESD during that event ?

    The only risk factor I am aware of is that there is a high inrush condition on this variant of the design when a large external capacitance is connected to the supply once it is up and which occurs on each startup cycle. 

    We don't recommend to have hot-pluggable load on the o/p as it can cause multiple switching and can stress the pull-down structure at the GATE. Is there a way you can avoid by having inrush limit circuit on the load side ?

    Best Regards,

    Rakesh

  • Hi Rakesh,

    We have a capacitive load which is switched in by a series PFET under software control after the main rail is established.

    We've significantly reduced the severity of this event for our next design iteration. It still occurs but the current surge is now not sufficient to trigger a circuit-breaker fault. I need to understand the level of risk for both the original and revised implementation.

    If you're concerned about this could you please suggest what/where I should be measuring to look for anything that could damage the device during the event? I have taken a lot of measurements during previous investigations into this area and haven't seen anything of concern yet.

    Do you have any prior experience or idea of what might have caused the fault I'm seeing - aside from the application query above?

    Thanks,

    Paul.

  • Hi Paul,

    I would need some more time to get back on this. I will reply by tomorrow. Sorry for the delay.

    Best Regards,

    Rakesh

  • Hi Paul,

    one scenario where I think that device can get stressed is that when you hot-plug the cap the LM5069 hits circuit breaker and output cap gets discharges through the diode and GATE pull-down circuit. There is a possibility to happen such events multiple times leading to partial failure of pull-down circuit.

    But surprisingly we have seen any change in impedance at the GATE pin from your measurements.

    I am on leave now and I can get back on further question in the early next week. Apologies for the inconvenience. 

    Best Regards,

    Rakesh

  • Hi Rakesh. 

    I observed that the CTIMER capacitor on this version of the design is 2u2F rather than the 470nF that we changed it to later and on which we've done much of our validation. The resistance change and insertion timer failure that we're left with would suggest an issue with this pin. Could this size of capacitance cause an issue for some reason??

    Paul

  • Hi Paul

    Apologies for getting back late on this.. 

    As we have seen difference in the impedances at the TIMER pin and the timer voltage is building up to 6V, I am suspecting that the 1.5mA current sink might have damaged. This might have kept the device in insertion time mode for infinite and not responding to even if we do UVLO reset.

    6V limit is due to the protection clamping circuit at the TIMER pin.

    I am discussing with the designer to understand which all scenarios can damage 1.5mA sink circuit. 

    If you get chance, can you test the failed unit by shorting the TIMER pin to GND through 1kOhm resistor after TIMER voltage reached 4V i.e., forcing the end of insertion interval.

    Best Regards,

    Rakesh

  • Thanks Rakesh. This aligns with my thoughts as to what has failed and I would be very interested to hear some theories as to how this might have happened.

    I'll try and run the test you suggested next week.

  • Hi Rakesh.

    We ran the test you suggested on the failed part/board. When the CTIMER pin reached ~4V during insertion delay we manually discharged it to 0V through a 1K resistor and then released it again.

    What we observed is that the GATE pin was unaffected and it just started to charge up to 6V again. We repeated the test with UVLO low and high.

    I did wonder whether it might be the voltage comparator on the CTIMER pin that's actually at issue rather than the discharge current source, such that the controller doesn't know when to engage the discharge and move on ...

  • Hi Paul,

    Thanks for testing at your end.

    I am about to reply with the feedback from my designer. We suspect two reasons for the timer to reach 6V, one we already discussed earlier is the failure of 1.5mA discharge current and another one is the comparator issue which you also pointed out. But, we are struggling to point out why a low voltage TIMER pin can get damage due to any supply line (on power side) disturbances. So, we don't think that comparator section has damaged but there might be some shift in the comparator reference thresholds.

    If you have all the necessary information for FA, please go ahead and raise request. We will push for further analysis.

    Just to rule out, Have you checked the same failed IC with lower value of timer cap (say 100nF) ?

    Best Regards,

    Rakesh

  • Hi Rakesh,

    We reduced the CTIMER cap to 100nF and there was no change on the failed device.

    I have raised return request CPR221067721 to return the device for failure analysis. If there's anything you can do to expedite the return process that would be appreciated.

    Paul.

  • Sure Paul. I will follow-up.

    Best regards,

    Rakesh 

  • Hi Paul,

    I am temporarily closing this thread as we are proceeding with FA.

    Best Regards,

    Rakesh