TPS16630 has protection features (such as OVP, thermal protection and current protection) which can shut down internal FET. It also has SHDN-pin to ON/OFF internal FET.
So internal FET is in ON-state when all the protection features are not asserted and SHDN-pin is pulled high, right?
For example, in the case that one of the faults is detected and SHDN-pin is pulled low, the internal FET is OFF.
And even if SHDN-pin is pulled high, the internal FET stays OFF until the fault is removed. Is my understanding correct?