UCC5870-Q1: triggering secondary side with nothing on primary side

Hi Daniel,

For point 1:

Thanks for explanation, it’s good to know that primary side faults might be latched and stored on the secondary. However, in tests that they are running now they never supply voltage to VCC1.

For point 2:

They've double checked the device that they are driving and confirmed that it can be actuated, so the voltage at the DESAT pin is basically correct. They must have rounded down to 0 V since there is some effective resistance in the path. See your point on higher priority faults. We are not sure which ones they might be triggering. Aside from internal fault things like regulators and SPI, they only see short circuit enabled by default. They saw that there was 0.5 V on AI2 in my measurement, so they thought it might be initially floating up to the default 1000 mV setting and tripping the SC fault, but they shorted AI2 to GND2 and it’s now 0 V, and it’s still not working.

Do they need to supply 4 V to VREF? They see it’s set by default to “external” supply and there is mention that it has its own current limit and UVLO/OVLO trips. Does it matter the order or slew in which AI5, AI6, VREF, and VCC1 rise to their nominal values?

As far as waveforms:

Which signals of interest so they can do a boot-up transient capture or something like that.

Thanks for the clarification Jeramie.

The order and slew rate shouldn't matter, I don't believe VREF needs to be powered, but I will double check that and get back to you tomorrow. I will also try to get waveforms demonstrating the test you are describing.

As to signals of interest, VCC2, AI5, AI6, and OUTH (Or the Gate of the switch) should be sufficient.

I will get back to you tomorrow.

Regards,

Daniel

Hi Jeramie,

I have gotten to the lab and confirmed what I had previously said. Vref does not need to be powered for secondary ASC, even though it defaults to External.

I was able to capture the below waveform in the lab. The primary side is unpowered, and the Source connection is shorted to GND to prevent DESAT from triggering (I was testing without connecting to an actual FET)

Please let us know if the customer continues to have trouble replicating this waveform.

Regards,

Daniel

Hi Daniel,

Here are some oscilloscope screen captures:

In this scenario (which is our intended use-case) I’m just providing around 15 V to VCC2, shorting AI5 and AI6 together and apply around 3.5 V, and leaving VREF with just a bypass capacitor. All measurements relative to GND2. AI2 is shorted to GND2. I checked the DESAT pin and during the start-up transient it never sees more than 0.5 V and is otherwise ~0 V. Not all screenshots have the same time or vertical divisions.

- 1 -



CH1 – VCC1

CH2 – AI5 & AI6

CH3 – OUTH

- 2 -

I’m including the next few waveforms just in case:

CH1 – VCC1

CH2 – AI5 & AI6

CH3 -- VBST

CH4 – OUTH

- 3 -

CH1 – VCC1

CH2 – AI5 & AI6

CH3 – VEE2

CH4 – OUTH

VEE2 is clamped to GND2 through a Schottky diode, but it looks like there is a transient that initially takes it above the recommended 0.3 V.

- 4 -

CH1 – VCC1

CH2 – AI5 & AI6

CH3 – VREG2

CH4 – OUTH

I know this is a little different from what I presented before (where VEE2 was powered), but I assume it would work this way as well?

Hi Jeramie,

Are you measuring the AI5 and AI6 pins directly at the pins, or is there a resistor/other components in between?

You say VREF is powered with 4V externally, does this power come up before AI5 and AI6 come up? 

Would you be able to repeat this test while applying 4V instead of 3.5V? I know your use case includes 3.5V, but I want to see if you can replicate my results in which I applied 4V. I will also try to get to the lab and test with 3.5V.

Regards,

Daniel

Jeramie, I have tested my board in the alb again and was able to control the secondary ASC with any AI5 and AI6 voltage above 3V. Could you share your schematic so I can look for any differences from my setup? If you don't want to post them publicly you can send me a private message.

-Daniel