Other Parts Discussed in Thread: UCD90160A, UCD90160,
There are two UCD90120 in the design since i have to monitor more than 13 voltage inputs. The two UCD90120 are cascaded. There is a master FPGA in the
Below are the requirements:
- UCD 1 sequence starts with nRESET going high. nRESET has a RC circuit. nRESET can also be controlled by FPGA.
- GPIO14 is used as power good to next UCD GPIO 17.
- UCD2 GPIO16 is used as Power good to FPGA as well as used to control the reset of SOC.
Is this circuit fine?
Please refer the attachment for the diagram.