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TPS3808: When does capacitor C_T get discharged?

Manuel Madlener
Prodigy 50 points
Part Number: TPS3808

Good day!

The exact part I have is TPS3808G30DBVR.

I am confused about the conditions under which the C_T-capacitor is discharged.

In the datasheet for TPS3808 it says that "When a \overline{RESET} is asserted, the capacitor is discharged." (page 11) and that "A logic low (0.3 VDD) on
\overline{MR} causes \overline{RESET} to assert."

Therefore, I would expect that the capacitor is discharged on falling edges of \overline{MR}.

However, this is not the case for the devices I have at hand: They discharge the capacitor on rising edges of \overline{MR} and on rising edges of \overline{RESET}. (See image below)

For completeness, I include here the circuit diagram:

 

Due to this behavior the reset delay time depends on the history of the MR-pin:

When MR has been long for a long time and then goes high: 15.56s (see measurement on the right side of the screenshot below)

 When MR was high, then low (for approx. 4s) and then goes high again: 14.28s. (screenshot below) Why is C_T here only discharged on the rising edge of \overline{MR} and not (as is written in the datasheet) already on the falling edge?

Thanks for your help!

Manuel

  • +1
    TI__Genius 11340 points

    Hi Manuel,

    Thank you for your question, I'll be happy to help. The 200nA current source that charges the capacitor is not enabled until the reset condition is cleared. Such as a raising edge on the \MR pin or the Voltage on the SENSE pin going above the threshold. Once the capacitor is charged to 1.23V, the \Reset will de-assert, and the capacitor is going to fully discharge disabling the 200nA current source to wait for the next event. What you're seeing on your first image is you "rebooting" the 200nA current source and recycling the charging the discharging process.

    The CT capacitor does no react on the assertion of the \MR but instead on the de-assertion.

    Jesse  

  • 0
    Prodigy 50 points

    Hi Jesse,

    Thanks a lot for your quick answer!

    What you are saying makes sense. But then it seems to me that the datasheet is incorrect or at least not very precise.

    In the datasheet it says that "A logic low (0.3 VDD) on \MR causes \RESET to assert." and "When a \RESET is asserted, the capacitor is discharged.",
    which implies the following:
    falling edge on \MR => \RESET  asserts => capacitor is discharged

    I guess the capacitor is only discharged when \overline{RESET} has a falling edge, but not when it is already low?

    Also the fact that the capacitor is discharged at the de-assert of \Reset is not specified in the datasheet, is it?

    So basically the datasheet says that the capacitor is discharged at the assertion of \Reset, while in reality the capacitor is discharged at the de-assertion of \Reset?

    Manuel

  • 0 in reply to Manuel Madlener
    TI__Genius 11340 points

    Hi Manuel, 

    Yeah the wording is a little confusing, but when the datasheet say  "When a \RESET is asserted, the capacitor is discharged." it is saying that the capacitor has no charge and not discharging at that given point. 

    Jesse