• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 63 subscribers
  • Views 115 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LM5122: About switch wave and soft-start

Peter Xu
Expert 3235 points
Part Number: LM5122
Other Parts Discussed in Thread: LM5022

Hi team,

I'm testing the EVM board of LM5122.And I got some question.

1. The sw wave rises with concussion. I wonder if it's because MOSFETs have parasitic capacitance.

2. In the 7.3.7 of datasheet, Vout remains at the Vin value for a period of time(Fig.22). However, in Fig.48 Vout rises directly to the rated value. Is there any confliction?

I'm sorry if I didn't describe precisely. Related pictures are attached.

Best regards,

Peter.

  • 0
    TI__Genius 11405 points

    Hi Peter,

    1. You will always see some spike at a sharp rising or falling edge. This is generally caused by the parasitic inductance and capacitance of the components.

    2. LM5022 send the first gate driver signal when SS(FB) is high than Vin/Vo*1.2V (Vfb after soft start), and Vo starts to ramp up. In Fig.22, The SS start to ramp up later than that in Fig.48. So, Vo stayed at Vin for a period.

    Best Regards,

    Feng Ji

  • 0 in reply to Feng Ji
    TI__Expert 3235 points

    Hi Feng,

    Thanks for you answer! But I'm confused about the second point: It seems like SS wave can rises earlier or later in different occasions. I wonder what causes the difference. Is it because of different input voltage wave?

    By the way, in datasheet it says the first gate driver signal is sent whenever SS reaches 1.2V, and you said it's Vin/Vo*1.2V. Did I miss something in datasheet?

    Best Regards,

    Peter

  • +1 in reply to Peter Xu
    TI__Genius 11405 points

    Hi Peter,

    SS ramp up is controlled by ULVO and other logic. So, the time when SS rises can be different.

    Sorry, I cannot find such sentence in the datasheet, would you point where it is? Actually, the gate driver is controlled by COMP, which is the output of the error amplifier.

    Best Regards,

    Feng Ji