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TPS7A20: SPICE model

Luca Vassalli
Prodigy 10 points
Part Number: TPS7A20
Other Parts Discussed in Thread: TPS7A02,

Hi,

I am using the TPS7A20285 LDO and simulating the effect of ESR of the output cap. 

I see the datasheet lists the output cap requirements as 0.47uF minimum and 100mohm max.

I downloaded the spice model on the product page and I did some simulations but I am not sure the model shows me the effect of output cap on the loop stability.

Since the model seems to be a generic model I think they only thing I had to modify was the V_out parameter (set to 2.85V in my case) but maybe I need to modify other parameters?

I attached my sim results which would show very stable response with 1mohm (dashed line) or 1 ohm (solid line), I tried with higher resistance (ESR) and it does not change much either. Can you check if the model includes this behavior, if not, do you have more details about the behavior with higher ESR? my application will be on the edge of the ESR limit and possibly even the cap min capacitance limit, I want to see how much margin I might have.

I will have the same question for the TPS7A0218 but that datasheet does not specify the min or max ESR, does it mean there is no limitation?

I already had a discussion with "Customer support" but they told me that EE support is a better forum for this, in caser you want to see here is the case # 

Case Number:  CS1189132

 

 

Thanks, LV

  • 0
    TI__Mastermind 37895 points

    Hi Luca,

    Our LDO PSPICE models are behavioral models and you will not see loop stability effects. 

    The upper (and lower) limit for ESR is usually for stability. I also don't see any upper limit for ESR for TPS7A02; there may be an upper limit eventually but since it wasn't specified I would expect it to be much higher than 100mΩ. 

    What is the output cap for your application? Are you constrained by board space?

    Regards,

    Nick

  • 0 in reply to Nick Butts
    Prodigy 10 points

    Thanks Nick for verifying,

    Yes I am very much constrained by board space as this will be a portable application. We are developing some capacitors ourselves to be used in customer application and our customer is using those LDOs. We will be at the edge of the minimum capacitance for the TPS7A20 0.47uF and 100mohm max as shown on table 6.3 and I am bumping up against both of these limits. We can certainly guarantee min capacitance and max ESR but we do not have much room to spare and are playing with tradeoffs, for example we might be at 400nF and 50mohm or 600nF and 200mohm (potentially violating one or the other spec but with guaranteed limits).

    I know you probably have margin on the numbers published in the datasheet and I know they will depend on the real operating conditions (including Vout and Iout). That's why I was hoping that the model would at least giving me some idea of what is more important, capacitance or ESR.

    Same goes for the TPS7A02, that one simply says 1uF recommended, but does not say min, necessary, can we also use 400nF and 100mOhm if transient is not a priority? (just stability). I know some LDO can be stable without output capacitors (as they have internal emulated Cout), but that's a visibility I do not have for the TI LDOs.

    Any guidance would be appreciated.

    Thanks, LV

  • 0 in reply to Luca Vassalli
    TI__Mastermind 37895 points

    Hi Luca,

    The minimum recommended value for the output capacitor includes 50% derating, but the 0.47uF minimum requirement is after derating, so if there is less than 0.47uF of effective capacitance the device will likely be unstable or marginally stable. 

    For TPS7A02 there is also a minimum 500nF effective capacitance requirement for stability. From the datasheet there is no indication that a slightly higher ESR will result in instability, so I would think that 600nF effective capacitance and 200mΩ ESR will work for it. 

    You are correct in that some devices do not require an output cap, but neither of these devices fall into that category. If they did not require an output cap for stability, the datasheet would state that.

    I suppose since you are developing your own cap for the customer's application, you don't have any flexibility other than 400nF, 50mΩ or 600nF, 200mΩ?

    Regards,

    Nick

  • 0 in reply to Nick Butts
    Prodigy 10 points

    HI Nick,

    we do have flexibility but as you can imagine it is all about size tradeoff. Also the numbers I quoted are after derating too.

    If I summarize we should be good with the following limit

    TPS7A02: 500nF and 200mOhm

    TPS7A20: 470nF and 100mOhm

    But if you tell me I can do 400nF and 200mohm (guaranteed) that would be a win win for everyone. Is there a way to ask the design team to verify that? (This is a high volume application .... let me know if I need to talk to "sales" directly to get an answer from the design team)

    Thanks,

    Luca

    and in case you want to know more about what we do: www.empowersemi.com/.../

  • 0 in reply to Luca Vassalli
    TI__Mastermind 37895 points

    Hi Luca,

    I can ask the design team if they can run some sims, but I'll need some more application requirements because as you mentioned, stability near the limits is going to depend on the load current and output voltage. What is the input voltage, output voltage, and load current? 

    I'm going to guess ahead of time that 400nF is not going to be enough. Even if the ESR was within the recommended range the device would be unstable, so I'm skeptical that it will work. With that said, depending on the load conditions it might be marginally stable, and if transient performance isn't important then maybe it can work. 

    Regards,

    Nick

  • 0 in reply to Nick Butts
    Prodigy 10 points

    ok here is what I have:

    TPS7A0218: Vin 3.1V (LI battery range), Vout 1.8V Iout 0-100mA

    TPS7A20285: Vin 3.1V (LI battery range), Vout 2.85V  Iout 0-150mA

    Thanks for the help

  • 0 in reply to Luca Vassalli
    TI__Mastermind 37895 points

    Hi Luca,

    Okay I sent a request to the design team in India that was responsible for this part. I'll update you when I have more information. 

    Regards,

    Nick

  • 0 in reply to Nick Butts
    Prodigy 10 points

    Hi Nick, any update? Thanks

  • 0 in reply to Luca Vassalli
    TI__Mastermind 37895 points

    Hi Luca,

    I haven't heard back from the design team yet, but I just sent another reminder. 

    Note that this will probably take some time to get results. I would estimate that if they started working on it now, we might have results in 1-2 weeks. If they don't have the manpower right now and have to delay the work, it would take longer.

    Regards,

    Nick