Other Parts Discussed in Thread: TPS7A16
Hi support team,
How do the TPS7A1601ADGNR and TPS7A1601DGNR differ in their intended use?
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TPS7A16A is a spin from TPS7A16A and there are some differences for the EN Voltage requirements and UVLO
TPS7A16A EN pin:
Compared to TPS7A16:
Also, notice the recommended slew rate for TPS7A16A. This question has been addressed several times before:
If the slew rate is less than the recommended 1.5V/us, then there should not be any issue using either device.
Thank you for your reply.
I have understood as follows.
・TPS7A16A is a spin-off from TPS7A16.
・The TPS7A16A has improved EN fast rising capability over the TPS7A16.
However, both recommend less than 1.5V/μs.
If possible, please let me know what kind of issues occur when EN rising is fast.
Thank you for your support.
Section 6.3 says "ramp-up", but section 7.3.1 says "rising and falling".
I'm wondering if I should be concerned about "falling".
Also, I can't find any mention of EN slew rate limits in the TPS7A16 datasheet SBVS171F.
It would be helpful if it was added to the datasheet.
I apologize for the delayed response.
I dont see why the fall time would be an issue, however, I am waiting response from the team to confirm this.
I will have to look into the data sheet and see how to include this, however, it does take some time to get a data sheet updated and published back to the web.
I got some feedback in regards this.
The main issue is when having a PWM as stated in section 7.3.1. When multiple pulses occur at these ramp rates, the device can enter test mode and pull Vout down.
This occurs if there is a Vin and EN sees multiple pulse, however, the falling edge should not have any impact. It is very common that the falling follows the rising edge, therefore the use of language here.
In regards the DS, yes I agree, having this information on the TPS7A16 is helpful as well. The time line to get a DS updated is sometimes lengthy, but I will see how to address this for future references.