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TPS272C45: No UVLO at Vdd=5V

Hans
Genius 12865 points
Part Number: TPS272C45

Hello Team,

Connections: VS=24V, Vdd=5V from external independent power supply; load at OUT1 is about 10mA

When disconnecting the 24V the VS pin should be 0V, correct? But is stays at 4.2V and the UVLO does not trigger.

Page 8 shows UVLOF for VS for Vdd between 3.0V and 3.6V; What are these values for Vdd=5V?

This behavior is independent of the logic state of the EN pin.

According data sheet Vdd can be 5V. How can be ensured that VS = 0V when Vdd = 5V is applied?

How can you ensure that the UVLOF is detected?

Thanks and Best Regards, Hans

  • 0
    TI__Genius 16390 points

    Hi Hans,

    You can check if device is in the UVLO state by applying HI signal for EN pin and check if you see VOUT to be the same as VS (if the FET has been turned on). If it's in UVLO state, the output should always stays at 0V. 

    One thing to check: is VS floating in this case when you observe 4.2V at VS? Could you check what the VS voltage is when applying 3.3V VDD?

    Also it would be good to share the schematics you have.

    Thanks!

    Regards,

    Yichi

  • 0 in reply to Yichi Zhang.
    TI__Genius 12865 points

    Hi Yichi,

    schematics are not available. Yes, VS is floating when seeing the 4.2V. With Vdd=3.3V VS is 0V. But I expect to see the same with Vdd=5V! Can you explain what could be wrong here, please?

    Thanks and Best Regards, Hans

  • 0 in reply to Hans
    TI__Genius 16390 points

    Hi Hans,

    I was testing on the EVM in the lab and see similar behavior - however the voltage at VS is lower. 

    I'm thinking there might be leakage path between VDD and VS internal to the device when VS is floating. 

    Is this a concern to customer? If so, could you ask customer to have external pull-down at VS?

    Regards,

    Yichi

  • 0 in reply to Yichi Zhang.
    TI__Genius 12865 points

    Hi Yichi, thanks for testing and confirmation. And yes, this is a concern. What R would you suggest as pull down? Does the voltage at VS  go down to zero with e.g 100k? Will we update the datasheet? 

    Thanks and Best Regards, Hans

  • 0 in reply to Hans
    TI__Genius 16390 points

    Hi Hans,

    I have not done testing on the value, but it will depend on the internal leakage path (how strong it is). I would suggest try 10k pull down first and see if the voltage level is acceptable, and adjust the resistor accordingly.

    I will align with the team and get more insights on this issue. If this is confirmed, then we will update the datasheet accordingly.

    Regards,

    Yichi

  • 0 in reply to Yichi Zhang.
    TI__Genius 12865 points

    Hi Yichi, 

    A 10k pull-down does not solve the problem.
    Measurements with a potentiometer connected to VS showed that a current of about 50mA is required to trigger UVLO. The resistance was 30 Ohm and the dissipated power results in 19W! 

    It is also questionable whether such a high current of 50mA can be carried via the Vdd pin.

    Please let me know how this problem can be solved and I think that this behavior needs to be reflected in the data sheet. Maybe by limiting Vdd to 3.3V.

    Thanks and Best Regards, Hans

  • 0 in reply to Hans
    TI__Genius 16390 points

    Hi Hans,

    Let me check with the team and get back to you on this.

    Thanks!

    Regards,

    Yichi

  • 0 in reply to Yichi Zhang.
    TI__Genius 16390 points

    Hi Hans,

    For now I don't have a good solution but use 3.3V VDD for now. Please feel free to open a new thread is customer is still concerning on this issue. Thanks!

    Regards,

    Yichi

  • 0 in reply to Yichi Zhang.
    TI__Genius 12865 points

    HI Yichi,

    that's what I suggested meanwhile. When can we expect to see an updated version of the data sheet as UVLO obviously does not work with Vdd=5V?

    Thanks and Best Regards, Hans

  • 0 in reply to Hans
    TI__Genius 16390 points

    Hi Hans,

    Thanks for the recommendations to the customer. We will keep investigate this issue and update you if a decision is made.

    Thank you!

    Regards,

    Yichi