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UCC21750-Q1: SiC MOSFET driving methods

Part Number: UCC21750-Q1
Other Parts Discussed in Thread: UCC21750, UCC21732

I am working on 11kW onboard charger project.

Need support on UCC21750-Q1 MOSFET driving method.

SiC MOSFETs can be driven by Zener diode method (for negative bias) & bootstrap method.

The datasheet of UCC21750-Q1 does not mention bootstrap driving method.

Can bootstrap driving be used with UCC21750-Q1?

If yes, to generate negative voltage Zener diode can be used or not?

What are the pros & cons of bootstrap vs Zener diode driving methods? 

Also, what's is the difference between DESAT & overcurrent protection?

Can you please suggest dual channel MOSFET driver having active miller clamp/ DESAT/ fault reporting features.

  • Hi Abhishek,

    Thanks for your interest in the UCC21750 device.

    1. Yes you can plan Bootstrap approach to create isolated bias.  There are 2 isolated biases needed [VDD - Pos] and [VEE- neg]. Zener diode can be used to generate the negative isolated bias from Isolated bias. It can be from Bootstrap approach or from other isolated bias planned. Hope it answers your question in terms of differences between these 2 approaches. more info about bootstrap circuitry here.

    2. Detailed APP note about different SC protection approach is here.

    3. Currently our single channel isolated drivers support different protection features- Single channel drivers comparison here. Our dual channel drivers comparison here - but don't have the protection feature. In case of full bridge circuit, we recommend 1 dual channel driver and 2 single channel isolated drivers on each leg to support protection on each of the legs.

    Hope it answers your question. 

  • Thanks for reply.

    As mentioned in point 3 in below quote, 

    In case of full bridge circuit, we recommend 1 dual channel driver and 2 single channel isolated drivers on each leg to support protection on each of the legs

    Can you please elaborate this. You meant to say two single channel drivers for high side & 1 dual driver for low side?

    Or 1 dual channel driver for half bridge & 2 single drivers for other half bridge.

    If possible pls share the reference schematic/design where such driver combination used. 

  • Hi Abhishek,

    2 single Ch isolated drivers with protection for high side & 1 dual Ch driver for low side and also It depends upon the system and the protection requirement.

    We have a reference design using UCC21732 - the same family as UCC21750. But this is not full bridge reference design. But it will give you idea about isolated bias and other protection feature implementation using UCC217xx device.

    You can also refer UCC21750 EVM Design file as well about how to incorporate the isolated driver.

    If it answers your question, please press the green button.

    Thanks

    Sasi

  • Hi thanks for reply.

    But want to know what are the pros & cons of bootstrap MOSFET driving method over without bootstrap method (isolated bias supply) ?

    Is bootstrap always preferred? 

  • Hi Abhishek,

    Bootstrap approach is one of the cost effective ways to generate High side bias with a diode, a resistor and a bypass capacitor. If designed appropriately as described in the app note shared ["bootstrap circuitry" ensuring appropriate cap, resistor and diode ], it will be suffice for the isolated bias requirement.

    Pos: Cost effective with few components and simple circuit to generate isolated bias.

    Few things to consider,

    1. The Bootstrap capacitor will get charged when the low side driver is switching, so need to consider if the application allows appropriate Low side "switch on" time.  

    2. Need to design appropriate C and R values so that the bootstrap supply provide required bias for all the needed load conditions, with minimum losses.

    Hope it answers your question.

    Thanks

    Sasi  

  • Hello Sasikala,

    I am using UCC21750-Q1 driver. In the bootstrap reference document Bootstrap Circuitry Selection for Half Bridge Configurations, there is following term that are not available for 21750.

    e.g. IHB = HB to Vss leakage current.

    The leakage current is for IH or IL i.e. on 5V side (Logic inputs IN+, IN-) mentioned in datasheet.

    Should we consider that current to calculate bootstrap cap value?

  • Hi Abhishek,

    The Cboot should support both the switching current [based on the Gate capacitance] + the device quiescent current max [for the entire period of switching Ton+Toff]

    IHBS is not the IH/IL logic inputs leakage current.  UCC21750's VDD leakage current spec [equivalent to HB Leakage] is not defined in the datasheet.

    If you plan to design biasing the device current [IVDDmax] + Current needed for the External gate capacitance [based on Power Switch gate charge], then it will fulfill your biasing need. Hope it helps.

    Also as recommended in the design, Cboot min >=  10xCg, this should help to design the Cboot.

    I recommend that you do simulations and prototyping for this design in your system to verify that it will function within the driver's limits.

    We also have a reference design for isolated Bias using UCC14240-Q1 - a single chip solution to create both Positive and Negative isolated bias for UCC217xx family of devices in the following link:

    Thanks

    Sasi

  • The DC_DC module UCC14240-Q1 that you suggested is for 24V system, our input range is 9-16V.

    I think the leakage current parameter should have been mentioned in the datasheet of UCC21750-Q1.

    Which tool/software is suitable for UCC21750-Q1 simulation? Pspice?

  • UCC21750 model in available for PSpice only -so you can simulate with PSPICE.