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TPS3808: Accuracy of reset delay time

Part Number: TPS3808

Good day!

What accuracy can be expected from the reset delay time (or the on-chip precision 220-nA current source)?

The min-typ-max values in the table in section 7.6 indicate a tolerance of +/-40%.

Is this the expected value for the accuracy over the whole range of delay times?

I.e. When I select a C_T capacitor based on the formula on page 11, the actual time delay will lie within +/-40% of the design value?

Does the accuracy depend on the duration of the reset dime delay?

I am mostly interested in the long delay range (around 10s), for which there are no min-typ-max values provided.

Is the accurace better/worse/the same for such long delay times?

Does the time delay change over the lifetime of the chip?

E.g. when I measure the delay directly after assembly of the PCB and then again 3 year later, will I measure the same delay time? Or does here again a tolerance of 40% apply?

Thanks a lot for your support!

Manuel

  • Hi Manuel,

    Thank you for your question. In application, the reset time delay is the time it takes for the CT capacitor to be charged to 1.23V by the 220nA current source. 

    The main factor to consider is the tolerance of the capacitor being used in this application. Since variation in capacitance will vary the charge time of the capacitor.

    The +/- 40% tolerance is used to account for other system factors, like parasitic capacitance and temperature, as well as guard bands for the device. 

    The maximum can be stipulated in Figure 7.3, which is roughly around 14sec of delay. While the min is stated to be 100pF in the datasheet.

     

    The accuracy of the time delay should be the same as it would be in lower time delay.

    As for the longevity of the accuracy of the device, the main factor would be the quality of the capacitor being used.

    If a proper capacitor is used, the time delay should stay consistent within a 3 year span.

    Jesse 

  • Hi Jesse

    Thanks a lot for the reply!

    I am very happy to hear that the main influencing factor is the capacitor!

    I spent quite some time looking into tolerance and ageing behavior of the capacitors I use.

    In the end I calculated an approximate tolerance of +/-15% over 20 years of product lifetime.

    So when I saw the +/-40% in the datasheet, I got a bit scared that any consideration about the capacitor tolerance is wasted due to the inaccurate TPS3808. But according to our explanation, most of the +/-40% does not come from the TPS3808 itself (but instead from the capacitors), which is reassuring.

    Can you maybe provide some tolerances on the 220nA current source and the 1.23V threshold?

    Or do you see another way to estimate the overall accuracy of the delay, when assuming specific capacitor properties?

    Basically my question is the following: My capacitors account for approx. +/-15% tolerance on the time delay over 20 years. Figure 7-4 provides values for the delay vs. temperature. For my temperature conditions (0-70°C), I get maybe +/-1% due to temperature. As my delay is in the order of 10s, the capacitor is around 2uF, which means that any parasitic capacitance on the PCB can be neglected. Accordingly, I would expect an overall tolerance in the order of +/-16%. Is this already a good estimate for the overall tolerance that will be achieved, or does the TPS3808 introduce further inaccuracies? How big will the overall tolerance be? 16% 20%? 40%? Impossible to tell?

    Thanks a lot for your support!

    Manuel

  • Hi Manuel,

    A typical recommendation for a worst case analysis for this device is 30% tolerance.

    As for the 220nA current source, designing for a 30% tolerance will account for the degrade of the current source for the lifetime of the TPS3808.

    Jesse 

  • Hi Jesse

    Thanks a lot for the information!!

    Manuel