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TPS386000: How should we overcome watchdog timer at startup

Scott Anderson2
Prodigy 30 points
Part Number: TPS386000
Other Parts Discussed in Thread: OMAPL138

We are having an issue overcoming the watchdog timer of the power supervisor during powering on our system. Are there any recommended ways of doing this correctly?

We have an OMAPL138 as our processor that can't in run BOOT mode. It is being reset every 600ms.

Current Schematic is below:

PD1_WD : A 600ms Pulse Train connected to a OMAP GPIO 

UARTBOOT_H : High when in program BOOT mode, Low when in run BOOT mode.

DBG_RST_SW : Active Low Physical RESET switch

CCU_RSTN : Connected to Enable line of V_Core Regulator, V_Core of OMAP

OMAP_RSTN : Connected to *RESET , master reset of OMAP

Please let me know if more details are needed. Thank You.

  • 0
    TI__Prodigy 500 points

    Hi Scott,

    Thank you for your question!

    May I ask the bootup time of the system?

    One solution that I can suggest right now includes using a FET to physically disconnect WDO using a GPIO pin from the MCU as seen in the following diagram.

    Another possible solution could be to assert the MR pin to force a reset1 assertion. As seen in the following timing diagram, asserting the MR pin will stop the internal timer, so WDO will remain high during this time. Would this work for your system?

    Please let me know if you have any questions or updates!

    Best Regards,

    Andrew Li