hi,
There is a equation like this in 9.1.2.2 Programmable Reset Delay-Timing
td=3.066 x Cct +0.5ms
if Cct=0.1nF, the td=0.8066ms
how can this match to this table? the typ td is already more than 5ms, but calculation gives less than 1ms
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hi,
There is a equation like this in 9.1.2.2 Programmable Reset Delay-Timing
td=3.066 x Cct +0.5ms
if Cct=0.1nF, the td=0.8066ms
how can this match to this table? the typ td is already more than 5ms, but calculation gives less than 1ms
Hello,
Your calculation appears to be correct. The table you are showing details timing when the CT pin is left open or tied to VDD. Once CT is connected to a capacitor the timing becomes dependent on the capacitance. I would like to bring you attention to Table 9-2 which shows examples of how reset delay timing changes depending on the value of capacitance placed at CT.
Regards,
Oscar Ambriz